LAB REPORT 3: Synthesis of counter using Verilog

Synthesis:
synthesis is the process of converting a high-level description of design into an
optimized gate-level representation.
After completing a successful verilog module the writer use this synthesis tool to
consider design constraints such as timing, area, testability, and power.
Synthesis of (l3_8bit_up.v):
Verilog Module:

After completing a satisfying simulation, we write the rtl script.

Finally we synthesize the netlist which will show how the counter would look like.

Using report code we could find the timing, power consumption etc. information
about the designed circuit.

We can write our gate level netlist and SDC constraints for physical design

Conclusion:
With the help of synthesis tool we could manage to get the gate level netlist from
the behavioral module of the counter. Before the invention of synthesis tool
designers had to get the gate level netlist, power consumption, delay information
using hand calculation which was quite challenging.