Chapter 1

Sequential Circuits

 Sequential circuits refer to the combinational logic circuits that consist of input variables
(X) and logic gates (or Computational circuits) along with the output variable (Z)
 A sequential circuit refers to a special type of circuit. It consists of a series of various
inputs and outputs.
 The outputs depend on a combination of both the present inputs as well as the
previous outputs. This previous output gets treated in the form of the present state. For
example, flip-flops, counter, register, clocks, etc.
 Sequential circuit has memory so output can vary based on input. This type of circuits
uses previous input, output, clock and a memory element.
 A sequential circuit can be basically contain only the memory element.

Types of Sequential Circuits

There are basically two types of sequential circuits:

1. Asynchronous sequential circuits

2. Synchronous sequential circuits

Asynchronous Sequential Circuits

The asynchronous sequential circuits don’t make use of the clock signals. This type of circuit is
operated through various pulses.
Synchronous Sequential Circuits
The clock signal performs the synchronization of the state of memory elements in the case of
synchronous sequential circuits. The output, in this case, is either stored in latches (memory
devices) or flip-flops. The output gets synchronized with the clock’s only positive edges or only
the negative edges.

Categories of Sequential Logic Circuits

Sequential logic circuits are divided into three categories like following.

 Event-Driven
 Clock Driven
 Pulse Driven

Event-Driven: Asynchronous circuits that can change the state immediately when enabled.
Asynchronous (fundamental mode) sequential circuit: The behavior is dependent on the
arrangement of the input signal that changes continuously over time, and the output can be
changed at any time (clockless).

Clock Driven: Synchronous circuits that are synchronized to a specific clock signal. Synchronous
(latch mode) sequential circuit: The behavior can be defined from the knowledge of circuits that
achieve synchronization by using a timing signal called the clock.

Pulse Driven: This is a mixture of the two that responds to the triggering pulses.
 CHAPTER 4
Q1. EXPLAIN BUS & MEMORY TRANSFER IN DETAIL.

BUS TRANSFER:

A bus structure is more efficient for transferring information between registers in a multi-
register configuration system. A bus consists of a set of common lines, one for each bit of
register, through which binary information is transferred one at a time. Control signals
determine which register is selected by the bus during a particular register transfer.

The following block diagram shows a Bus system for four registers. It is constructed with the
help of four 4 * 1 Multiplexers each having four data inputs (0 through 3) and two selection
inputs (S1 and S2).
Bus Transfer using three-state buffer

Three State Buffer helps us generate a common bus. Here the three-state gates are similar to
the digital circuit having three gates. Here the first two are similar to having logic 0 and 1. The
third gate is in a state of high impedance.

 The outputs of four buffer are connected together to form a single bus line.
 No more than one buffer may be in the active state at any given time(2 X 4 Decoder).

MEMORY TRANSFER:

There are two memory operations in memory transfer:

READ OPERATION

The transfer of data from the Address Register into the Memory Buffer Register is known as the
Read Operation. The read operation is represented by MBR ← [AR] M . It states that the
Memory Unit M is transferred from [AR] representing Address register to Memory Buffer
Register (MBA).

WRITE OPERATION

Write Operation is the transfer of new data into the memory. The write operation is denoted by
[AR] M ← R1. It states that the Memory M from Register R1 is transferred to Address
Register([AR]).
 CHAPTER 5
Q. EXPLAIN ALL 8 TYPES OF REGISTER.

Data Register (DR)

Data Register or DR is used to stores the data that is written to memory or read from memory.
Mainly DR is used to transfer the data between CPU and memory. It will work in conjunction
with Memory Address Register as it specifies the memory location that the CPU wants to
access.

Accumulator Register (AC)

Accumulator Register is used to store the result of logical and arithmetic operations. This is also
used as a temporary storage location for the data during the calculations. This is commonly
used by every computer as they provide dedicated memory locations for storing the data and
results of the logical and arithmetic calculations and operations.

Instruction Register (IR)

The IR or Instruction Register stores the instruction that is currently in execution. The CPU
mainly uses IR to get the instruction, decode it and decide which operations have to be
performed to execute the instruction. It is a fixed-size register hence it stores only one register
at a time.

Temporary Register (TR)

The intermediate result of the calculations is stored in these registers. There is not any specific
purpose for temporary registers so they can be used for any purpose by the CPU and because
of this they also sometimes refer to as the general-purpose register. It can also be used to store
the intermediate data between many calculations or complex calculations.

Address Register (AR)

The Address Register or AR is used to hold the memory address of the data that the CPU wants
to read or write to. The CPU uses AR to specify the memory location that it wants to access. The
Memory Data Register (MDR) is used in conjunction with the AR to transfer the data between
the CPU and memory.
Program Counter (PC)

The program counter or PC is used to hold the memory address of the next instruction that has
to be executed. This will not remain constant as it is automatically updated by the CPU after
each instruction is executed. The CPU will increment it by 1. This will allow the CPU to control
the flow of the program. PC can be considered an important part of the CPU’s instruction-
fetching and execution cycle.

Input Register (INPR)

Input register is used to store the input that is given to the CPU from an external device or
source like a mouse or keyboard. This is mainly used in conjunction with I/O(Input/ Output)
instructions that transfer the data between external devices and the CPU.

Output Register (OUTR)

This register shows the output from the CPU to an external device, such as a printer or monitor.
It is used in conjunction with the input/ Output instructions to transfer the data between
external devices and the CPU. It is also used to store the data temporarily that is to be shown as
output so the CPU can continue to execute further.
 CHAPTER 7
Q1. EXPLAIN CONTROL MEMORY USING DIAGRAM.

Memory that is part of control unit is called control memory. Each word in control memory
contains microinstruction. A sequence of microinstructions creates a micro-program. The
control memory is assumed to be a ROM.
During the execution of a program, the control unit fetches instructions from the main memory
them to generate the necessary micro-instructions. These microinstructions then direct the
operation of other parts of the CPU and the overall functioning of the computer. The control
memory consists of micro-programs that are fixed and cannot be modified frequently
CONTROL UNIT:

The function of the control unit is to initiate sequences of micro-operations. There are two
major types of Control Unit:

 Hardwired Control:
When control signals are generated by hardware, the control unit is hardwired.
 Micro-programmed Control:
When control signals originate in data stored in a special unit and constitute a program
on the small scale, the control unit is micro-programmed.
CONTROL WORD:

The string of control variables which control the sequence of micro-operations is called a
control word. The control variables at any given time can be represented by a string of 1’s and
0’s.
MICROPROGRAMED CONTROL UNIT:

A control unit whose binary control variables are stored in memory is called a micro-
programmed control unit.
Q2. EXPLAIN DESIGN OF CONTROL UNIT.

The Control Unit is classified into two major categories:

 Hardwired Control
 Micro-programmed Control

HARDWIRED CONTROL:

In the hardwired control the control logic is executed with gates, flip-flops, decoders, and other
digital circuits. It can be optimized to make a quick mode of operation. In the micro-
programmed organization, the control data is saved in the control memory.

The control memory is programmed to start the needed sequence of micro-operations. A

hardwired control requires changes in the wiring among the various elements if the design has
to be modified or changed.

The block diagram of the control unit is displayed in the following figure. It includes two
decoders, a sequence counter, and several control logic gates.

Control unit of Basic computer:

MICROPROGRAMMED CONTROL:

In Micro-programmed Control, the micro-operations are performed by executing a program

consisting of micro-instructions.

BLOCK DIAGRAM:

 The Control memory address register specifies the address of the micro-instruction.
 The Control memory is assumed to be a ROM, within which all control information is
permanently stored.
 The control register holds the microinstruction fetched from the memory.
 The micro-instruction contains a control word that specifies one or more micro-
operations for the data processor.
 While the micro-operations are being executed, the next address is computed in the
next address generator circuit and then transferred into the control address register to
read the next microinstruction.

Microprogrammed control unit of Basic computer:

Q3. DISCUSS MICROPROGRAM SEQUENCER.

The task of Microinstruction sequencing is done by Microprogram sequencer. The address

selection part is called microprogram sequencer. Two imp factors that must be considered
while designing the microinstruction sequencer: The size of the microinstruction and the
address generation time.

Components of microprogrammed sequencer:

 CAR – Control Address Register

 SBR – Subroutine Register
 CD – Condition
 BR -Branch
 MUX Multiplexers

The purpose of microprogram sequencer is to present an address to the control memory so

that a microinstruction may be read and executed. The next address logic of the sequencer
determines the specific address source to be loaded into the CAR. The choice of the address
source is guided by the next address information bits that the sequencer receives from the
present microinstruction. The control memory is included in the diagram to show the
interaction between the sequencer and the memory attached to it. There are two multiplexers
in the circuit, first multiplexer selects an address from one of the four sources and routes it into
the CAR. The second multiplexer tests the value of a selected bit, and the result of the test is
applied to an input logic circuit.
 CHAPTER 8
Q4. DEFINE GENERAL REGISTER ORGANIZATION & EXPLAIN BUS ORGANIZATION FOR 7 CPU
REGISTERS.

GENERAL REGISTER ORGANIZATION:

Intermediate data is needed to be stored like pointers, counters, return address, temp results,
and partial products. Cannot save them in main memory because their access is time
consuming. It is more efficient and faster to be stored inside processor. So, the solution is
designing multiple registers inside processor and connect them through a common bus. In Basic
Computer, there is only one general purpose register, the Accumulator (AC) but in modern
CPUs, there are many general purpose registers. It is advantageous to have many registers.
Transfer between registers within the processor is relatively fast.

BUS ORGANIZATION FOR 7 CPU REGISTERS.

2 MUX : selects one of 7 register or external data input by SELA and SELB

BUS A and BUS B : form the inputs to a common ALU

ALU : OPR determine the arithmetic or logic microoperation

3 X 8 Decoder : select the register (by SELD) that receives the information from ALU

Binary selector input :

1. MUX A selector (SELA) : to place the content of R2 into BUS A

2. MUX B selector (SELB) : to place the content of R3 into BUS B
3. ALU operation selector (OPR) : to provide the arithmetic addition R2 + R3
4. Decoder selector (SELD) : to transfer the content of the output bus into R1

Control Word

 Encoding of Register Selection Fields :

 SELA or SELB = 000 (Input) : MUX selects the external input data.
 SELD = 000 (None) : No destination register
 Encoding of ALU Operation (OPR)
Q5. EXPLAIN STACK ORGANIZATION IN DETAIL.

Stack organization is a fundamental concept in computer architecture and programming that

involves the management of memory using a Last-In-First-Out (LIFO) data structure. A stack is a
specialized form of data storage that operates on the principle of pushing and popping
elements.

The push operation involves the following steps:

 Check if the stack is full.

 If not full, increment the top pointer and place the new element at the updated top
position.
 Store the element's value and update the top pointer.

The pop operation involves the following steps:

 Check if the stack is empty.

 If not empty, retrieve the element at the top position.
 Decrement the top pointer.
 Return the retrieved element.
 In addition to push and pop, other stack-related operations include peek and isEmpty
1. REGISTER STACK:

A register stack is a specialized type of hardware structure within CPU that facilitates
efficient register management and context switching. Registers are small, fast memory
locations that hold data that the CPU uses for immediate calculations and operations.

PUSH Operation

SP ← SP + 1

M[SP] ← DR

IF (SP = 0) then (FULL ←1)

EMPTY ←0

POP Operation

DR ←M[SP]

SP ← SP - 1

If (SP = 0) then ( EMPTY ←1)

FULL ←0
2. MEMORY STACK:

A memory stack is a data structure used in computer architecture for managing memory in
a Last-In-First-Out (LIFO) manner. It operates as a storage area where data is organized in a
way that the most recently added item is the first to be removed.

PUSH Operation

SP ← SP - 1

M[SP] ← DR

POP Operation

DR ←M[SP]

SP ← SP + 1

3. RPN (Reverse Polish Notation):

The reverse polish notation in the stack is also known as postfix expression. Here, we use
stack to solve the postfix expression.

A * B + C * D → AB * CD * +
Q6. EXPLAIN DATA TRANSFER & MANIPULATION.

Most computer instructions can be classified into three categories:

 Data transfer instruction

 Data manipulation instruction
 Program control instruction
1. DATA TRANSFER INSTRUCTION:
Load: transfer from memory to a processor register, usually an AC (memory read)
Store: transfer from a processor register into memory (memory write)
Move: transfer from one register to another register
Exchange: swap information between two registers or a register and a memory word
Input/Output: transfer data among processor registers and input/output device.
Push/Pop: transfer data between processor registers and a memory stack.
8 Addressing Mode for the LOAD Instruction:
@: Indirect Address
$: Address relative to PC
#: Immediate Mode
( ): Index Mode

2. DATA MAIPULATION INSTRUCTION:

Data manipulation instructions perform operations on data and provide the
computational capabilities for the computer. The data manipulation instructions in a
typical computer are usually divided into three basic types:
 Arithmetic Instructions:
The four basic arithmetic operations are addition, subtraction, multiplication,
and division. Most computers provide instructions for all four operations. The
increment instruction adds 1 to the value stored in a register or memory word.
The decrement instruction subtracts 1 from a value stored in a register or
 memory word. The instruction "add with carry" performs the addition on two
operands plus the value of the carry from the previous computation. Similarly,
the "subtract with borrow" instruction subtracts two words and a borrow which
may have resulted from a previous subtract operation. The negate instruction
forms the 2' s complement of a number, effectively reversing the sign of an
integer when represented in the signed-2's complement form.

 Logical and Bit Manipulation Instructions:

Logical instructions perform binary operations on strings of bits stored in
registers. They are useful for manipulating individual bits or a group of bits that
represent binary-coded information. The AND instruction is used to clear a bit or
a selected group of bits of an operand. The OR instruction is used to set a bit or a
selected group of bits of an operand. Similarly, the XOR instruction is used to
selectively complement bits of an operand. Individual bits such as a carry can be
cleared, set, or complemented with appropriate instructions.

 Shift Instructions:
Instructions to shift the content of an operand are quite useful and are often
provided in several variations. Shifts are operations in which the bits of a word
are moved to the left or right. The logical shift inserts 0 to the end bit position.
The end position is the leftmost bit for shift right and the rightmost bit position
for the shift left. The arithmetic shift-right instruction must preserve the sign bit
 in the leftmost position. The sign bit is shifted to the right together with the rest
of the number, but the sign bit itself remains unchanged. This is a shift-right
operation with the end bit remaining the same. The arithmetic shift-left
instruction inserts 0 to the end position and is identical to the logical shift-left
instruction. The rotate instructions produce a circular shift. Bits shifted out at
one end of the word are not lost as in a logical shift but are circulated back into
the other end.

3. PROGRAM CONTROL INSTRUCTION:

 Program Control Instruction:
Branch and Jump instructions are used interchangeably to mean the same thing.
 Status Bit Conditions:
The bits are set or cleared as a result of an operation performed in the ALU.
 4-bit status register:
Bit C (carry): set to 1 if the end carry C8 is 1
Bit S (sign): set to 1 if F7 is 1
Bit Z (zero): set to 1 if the output of the ALU contains all 0’s
Bit V (overflow): set to 1 if the exclusive-OR of the last two carries (C8 and C7) is equal to
1
Q7. WHAT IS PROGRAM CONTROL?

Program Control refers to the order and timing of instructions in a program. This includes the
order in which they are fetched from memory and the order in which they are executed.
Instructions can be executed in any order, depending on the program. However, there are
certain rules that must be followed in order to ensure that the instructions are executed
correctly and efficiently.

4-bit status register

Bit C (carry) : set to 1 if the end carry C8 is 1

Bit S (sign) : set to 1 if F7 is 1

Bit Z (zero) : set to 1 if the output of the ALU contains all 0’s

Bit V (overflow) : set to 1 if the exclusive-OR of the last two carries (C8 and C7) is equal to 1

CALL

SP ← SP - 1

M[SP] ← PC

PC ← Effective Address

RETURN
PC ← M[SP]
SP ← SP + 1
Q8. EXPLAIN TYPES OF INTERUPT.

There are 3 types of interrupts:

External Interrupts

The External Interrupt occurs when any Input and Output Device request for any Operation and
the CPU will Execute that instructions first For Example When a Program is executed and when
we move the Mouse on the Screen then the CPU will handle this External interrupt first and
after that he will resume with his Operation.

Internal Interrupts or TRAP

The Internal Interrupts are those which are occurred due to some problem in the execution for
example when a user performing any operation which contains any sort of error. So Internal
Interrupts are those which occur by some operations or by some instructions and the
operations those are not possible, but a user is trying for that Operation.

Software Interrupts

The Software Interrupts are those which are made some call to the system for example while
we are processing some instructions and when we want to execute one more application
programs.
 CHAPTER 9
Q9. EXPLAIN INSTRUCTION PIPELINING BRIEFLY.

Pipeline processing can occur not only in the data stream but in the instruction stream as well.
Most digital computers with complex instructions require instruction pipeline to carry out
operations like fetch, decode and execute instructions. In general, the computer needs to
process each instruction with the following sequence of steps.

1)Fetch the instruction from memory

2) Decode the instruction

3) Calculate the effective address

4) Fetch the operands from memory

5) Execute the instruction

6) Store the result in the proper place

Four-segment CPU pipeline

 FI: Instruction Fetch

 DA: Decode Instruction & calculate EA
 FO: Operand Fetch
 EX: Execution

Segment 1: The implementation of the instruction fetch segment can be done using the FIFO or
first-in, first-out buffer.

Segment 2: Memory instruction is decoded, and the effective address is then determined in a
separate arithmetic circuit.

Segment 3: Some operands would be fetched from memory.

Segment 4: The instructions would finally be executed in the very last segment of a pipeline
organization.
 CHAPTER 11
Q10. EXPLAIN ASYNCHRONOUS DATA TRANSFER IN DETAIL.

Asynchronous data transfer enables computers to send and receive data without having to wait
for a real-time response. With this technique, data is conveyed in discrete units known as
packets that may be handled separately.

Classification of Asynchronous Data Transfer

Strobe Control Method:

Strobe control method synchronizes data flow between two devices. Bits are transmitted one at
a time. To properly receive the data, the receiving equipment needs to be able to synchronize
with the transmitting device. Strobe control involves sending data along with strobe signal. The
strobe signal alerts the receiving device that the data is valid and ready to be read. The
receiving device waits for the strobe signal before reading the data to ensure sure it is
synchronized with its clock.

 Source initiated strobe

 Destination initiated strobe

Handshaking Method:

During an asynchronous data transfer, two devices manage their communication using
handshaking. It is guaranteed that the transmitting and receiving devices are prepared to send
and receive data. Handshakes are essential in asynchronous communication since there is no
clock signal to synchronize the data transfer.
During handshaking, we use two types of signals mostly they are request-to-send (RTS) and
clear-to-send (CTS). The receiving device is notified by an RTS signal when the transmitting
equipment is ready to provide data. The receiving device responds with a CTS signal when it is
ready to accept data.

 Source initiated handshaking

 Destination initiated handshaking

Q11. EXPLAIN I/O PROCESSOR (IOP) IN DETAIL.

IOP:

An input-output processor (IOP) is a processor with direct memory access capability. The
computer system is divided into a memory unit and number of processors. Each IOP controls
and manage the input-output tasks. The IOP is similar to CPU except that it handles only the
details of I/O processing. The IOP can fetch and execute its own instructions. These IOP
instructions are designed to manage I/O transfers only.

BLOCK DIAGRAM:

The CPU processes the data required for solving the computational tasks. The IOP
provides a path for transfer of data between peripherals and memory. The CPU assigns the
task of initiating the I/O program. The IOP operates independent from CPU and transfer
data between peripherals and memory.
Input/Output Channels

A channel is an independent hardware component that co-ordinate all I/O to a set of

controllers. Computer systems that use I/O channel have special hardware components that
handle all I/O operations. Channels use separate, independent and low cost processors for its
functioning which are called Channel Processors. Channel processors are simple, but contains
sufficient memory to handle all I/O tasks. When I/O transfer is complete or an error is
detected, the channel controller communicates with the CPU using an interrupt, and
informs CPU about the error or the task completion. Each channel supports one or more
controllers or devices.
 CHAPTER 12
Q12. WHAT IS MAIN MEMORY?

The main memory acts as the central storage unit in a computer system. It is a relatively large
and fast memory which is used to store programs and data during the run time operations. The
primary technology used for the main memory is based on semiconductor integrated circuits.
The integrated circuits for the main memory are classified into two major units.

RAM (Random Access Memory) integrated circuit chips:

RAM is the main memory of a computer. Its objective is to store data and applications that are
currently in use. The operating system controls the usage of this memory. It gives instructions
like when the items are to be loaded into RAM, where they are to be located in RAM, and when
they need to be removed from RAM.

ROM (Read Only Memory) integrated circuit chips:

In each computer system, there should be a type of memory that is fixed and unaffected by
power failure. This type of memory is known as Read-Only Memory or ROM.

 SRAM
RAMs that are made up of circuits and can preserve the information as long as power is
supplied are referred to as Static Random Access Memories (SRAM). SRAM consists of
an array of flip-flops, a large number of flip-flops are needed to provide higher capacity
memory. Simpler flip-flop circuits and MOS transistors are used for SRAM.
 DRAM
SRAMs are faster but their cost is high because their cells require many transistors.
RAMs can be obtained at a lower cost if simpler cells are used. A MOS storage cell based
on capacitors can be used to replace the SRAM cells. Such a storage cell cannot preserve
the charge and must be recharged periodically. Therefore, these cells are called dynamic
storage cells.
Q13. WHAT IS CACHE MEMORY?

Cache Memory is a high-speed memory. The cache is a smaller and faster memory that stores
copies of data from frequently used main memory locations. There are various different
independent caches in a CPU, which store instructions and data. The most important use of
cache memory is that it is used to reduce the average time to access data from the main
memory.

CACHE MAPPING: There are three different types of mapping used for the purpose of cache
memory which is as follows:

Direct Mapping

Direct mapping assign each memory block to a specific line in the cache. If a line is previously
taken up by a memory block the old block is trashed. An address space is split into two parts
index field and a tag field. The cache is used to store the tag field whereas the rest is stored in
the main memory. Direct mapping`s performance is directly proportional to the Hit ratio.

Associative Mapping

In this mapping, any block can go into any line of the cache. This enables the placement of any
word at any place in the cache memory. It is considered to be the fastest and most flexible
mapping form. In associative mapping, the index bits are zero.

Set-Associative Mapping

This is an enhanced form of direct mapping where the drawbacks of direct mapping are
removed. Set associative addresses the problem of possible thrashing in the direct mapping
method. It does this by saying that instead of having exactly one line that a block can map in
the cache, we will group a few lines together creating a set. Then a block in memory can map to
any one of the lines of a specific set. Set associative cache mapping combines the best of direct
and associative cache mapping techniques.

Q14. WHAT IS VIRTUAL MEMORY?

Virtual memory is a memory management technique that creates an illusion of a larger main
memory for the computer system. Virtual memory is a crucial component of a computer's
architecture, providing the ability to run larger applications and multiple programs
simultaneously, even if the physical memory (RAM) is limited.

Address mapping using Paging:

The address mapping is simplified if the information in the address space and the memory
space are each divided into groups of fixed size. The physical memory is broken down into
groups of equal size called page frames and the logical memory is divided into pages of the
same size. The programs are also considered to be split into pages. Pages commonly range from
2K to 16K bytes in length. In order to do the mapping, the virtual address is represented by two
numbers: a page number and an offset or line address within the page.

Page Replacement:

The FIFO algorithm chooses to replace the page that has been in memory for the highest time.
Every time a page is weighed into memory, its id-number is pushed into a FIFO stack. FIFO will
be complete whenever memory has no more null blocks. The page to be removed is simply
determined because its id-number is at the top of the FIFO stack. The FIFO replacement policy
has the benefit of being simple to execute. It has the drawback that under specific
circumstances pages are removed and loaded from memory too frequently.

CHAPTER 13
Q15. DISCUSS TIME-SHARED COMMON BUS.

Time-shared Common Bus:

The time shared bus provides a common communication path connecting all the functional
units like processor, memory unit etc. A processor can use bus only when the bus is free. The
sender processor puts the address of the destination on the bus & the destination unit
identifies it. In order to communicate with any functional unit, a command is issued to tell that
unit, what work is to be done. The other processors at that time will be either busy in internal
operations or will sit free, waiting to get bus.

Q16. EXPLAIN INTERPROCESSOR COMMUNICATION & SYNCHRONIZATION.

1. INTERPROCESSOR COMMUNICATION:

Interprocessor communication is a method that allows processes to communicate with each

other. This communication could involve a process letting another process know that some
event has occurred or the transferring of data from one process to another.

 shared memory : tightly coupled system

 Accessible to all processors : common memory
 Act as a message center similar to a mailbox
 no shared memory : loosely coupled system
 message passing through I/O channel communication

2. INTERPROCESSOR SYNCHRONIZATION:

Synchronization is a necessary part of interprocess communication. It is either provided by the

interprocess control mechanism or by the communicating processes. Some of the methods to
provide synchronization are as follows:

MUTUAL EXCLUSION:

Mutual Exclusion requires that only a single process thread can enter the critical section one at
a time. This also helps synchronize and prevents the race condition by creating a stable state.

MUTUAL EXCLUSION WITH SEMAPHORE

 Critical Section:
Once begun, must complete execution before another processor accesses
 Semaphore:
Indicate whether or not a processor is executing a critical section
 Hardware Lock:
Processor generated signal to prevent other processors from using system bus

SEMAPHORE:

Semaphore is a type of variable that generally controls the access to the shared resources by
several processes. Further, Semaphore is divided into two types as follows:

 Binary Semaphore: A binary semaphore is limited to zero or one. It could be used to

control access to one resource.
 Counting Semaphore: Counting semaphore may take any integer value. It could be used
to control access to resources having many instances.