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MEKELLE UNIVERSITY
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MEKELLEINSTITUTE OF TECHNOLOGY

Computer Organization And Architecture [COA] Mid Term Exam.

Weight 30%

Time given 2 hours

Date December 28, 2018

Full Name ____________________________ ID ____________ dep’t _______

Instructions
 Make sure 2 pages
 Cheating in exam is forbidden

Mekelle Institute Of Technology Semster I : Mid Examination Page 1

Part I: Short Explanation Questions[3pts each]
1) Explain how processor is enabling program execution. Describe difference between program, and
instruction.

 CPU is executing programs through fetch decode execute cycle. To makes the program
execution faster CPU can has multitasking principle that while the first instruction is
executing the next instruction will be loaded (fetched from memory).

 Here, program is collection of instructions but instruction is one state of execution by

processor.

2) Explain the differences between vonNeumann versus Harvard architecture. Sketch diagrams for
each of these structures.

 The abandon architecture vonneuman is when the data and address buses are connected in
the same line of transfer but with scheduling transfer.
 Harvard architecture notices that data and address buss are in separate line of connections
so that data and address will be transferred at the same time

3) Explain how registers communicate with memory busses.

Dues to set of complexities happen to connect register each other.

 Have one centralized set of circuits for data transfer – the bus. Have control circuits to select
which register is the source, and which is the destination

 Bus is a path (of a group of wires) over which information is transferred, from any of several
sources to any of several destinations. Transfer will be possible From a register to bus or
among registers: BUS  R

Mekelle Institute Of Technology Semster I : Mid Examination Page 2

Part II: Long Explanation Question[4pts each]
1) Suppose an architecture where address bus is 32 bits, data bus is 16 bits. As a programmer of java
code lets integer size is 8 bits. Draw a memory layout if you enter decimal number “243435”. Let
for simplicity starting memory address is 00000008.

For simplicity Answer sheet, The decimal number 243435 is 18 bit number as follows = 11 1011
0110 1110 1011

If size of data bus is 16 bit, this implies that 16 bit data will be transferred from memory to CPU
(registers) at once (clock time of the processor).

Hence, it is expected to say that the other two bits of the decimal number above will be
stored/read in the next instruction call.

00000008H stores 1011 0110 1110 1011

00000009H stores 0000 0000 0000 0011

Unfortunate due to size of integer data size is 8 bits here, the maximum integer number we can
accept in java is 28=256. The integer number we gave to java compiler will run overflow error.

2) Let you have calculator application in your system. You let open the application and you type
2+7
= 9. Answer the following Questions
i. Explain what is function of Operating system here
ii. Explain what is function of CPU here
iii. Explain what is the function of RAM here

OS is a system program in our computer that manages every hardware and software
resources. OS allows application programs to run over it. Here, CALCULATOR
application with its Graphical user interface/view and set of active buttons is developed
and then installed as part of the OS.

CPU is worker of OS that it will call by OS as one resource. To execute the addition of
2+7, CPU would use through ALU and CU.

RAM will load/read and store/write the result executed by CPU ALU, CU, and registers.
Here, one register stores value 2, another register stores value 7. The result/sum is stored
in Accumulator register by default. And then the value will transfer to RAM to display in
calculator Application.

Mekelle Institute Of Technology Semster I : Mid Examination Page 3

 3) The following is 8085 Assembly code. Answer the following Questions.

i. Describe the difference between registers, and instructions

Register is a small storage device that stores bits of data for operation. Registers can be
special and general purpose registers. Instructions are software commands that order the
CPU to do some operations. Instructions enable value of registers to be adjusted
accordingly. For example, ADD B is 8085uP instruction that adds contents of register A
and register B and then store the result in register A.

ii. Describe and list what are general and specific purpose registers.

GP Registers: will function on usual arithmetical and logical operations made by CPU.
Examples Accumulator (A/ACC), BC, HL, DE, etc
SP Registers: will function and called on some special purpose activities by CPU.
Examples MAR< MDR, IR, IRR, PC, SP (stack pointer)

iii. What would be value of MAR and MDR based on the above code

STA instruction stores/writes the value, previously at register A in to memory address

2900H. Here, MAR stores the address in which processor wants to put data in it and
MDR stores the value of that address (content=05)
Thus MAR = 2900. MDR = 0005H are values before updating.

Consecutive running of programs makes updates on register values. LDA instruction

loads/reads data (05) from memory location 2900.

Thus MDR =0005H, MAR = 2900H.

iv. Explain the purpose of Instruction register(IR)

The instruction register (IR) or current instruction register (CIR) is the part of a CPU's
control unit that holds the instruction currently being executed or decoded. IR has three
modes to identify the type of operation is memory mode, register mode and I/O mode.

Hence, in this example once the PC (program counter register holds address of execution
instructions sequentially, IR holds each of above sequential instructions their address is
hold by PC.

Mekelle Institute Of Technology Semster I : Mid Examination Page 4

 4) Suppose you have small bag. The bag can be Opened and Closed According to set of 4 buttons -
B1, B2, B3, B4. The BAG be open if you press two (2) of any consecutive buttons but the Second
(B2) button must stayed pressed. Design Open (OP) and Close (CL) logic circuit for this
scenario.

The truth table LOOKS like:

s.N B1 B2 B3 B4 OP CL
0 0 0 0 0 0 1
1 0 0 0 1 0 1
2 0 0 1 0 0 1
3 0 0 1 1 0 1
4 0 1 0 0 0 1
5 0 1 0 1 0 1
6 0 1 1 0 1 0
7 0 1 1 1 1 0
8 1 0 0 0 0 1
9 1 0 0 1 0 1
10 1 0 1 0 0 1
11 1 0 1 1 0 1
12 1 1 0 0 1 0
13 1 1 0 1 1 0
14 1 1 1 0 1 0
15 1 1 1 1 1 0

 Open Circuit OP = B2B3 + B2B3B4 + B1B2 + B1B2B4 + B1B2B3 + B1B2B3B4

 B2B3(1+B4) + B1B2(1+B4)+B1B2B3(1+B4) = B2B3 + B1B2 + B1B2B3

 B2(B3+B1+B1B3) = B2(B1+B3(1+B1))  B2(B1+B3)

 And CL = B1’B2’B3’B4’ + B1’B2’B3’B4 + B1’B2’B3B4’+ B1’B2’B3B4 + B1’B2B3’B4’

+ B1’B2B3’B4 + B1B2’B3’B4’ + B1B2’B3’B4 + B1B2’B3B4’ + B1B2B3’B4’

 B1’B2’B3’(B4’+B4) + B1’B2’B3(B4’+B4) + B1’B2B3’(B4’+B4) + B1B2’B3’(B4’+B4) +

B1B2’B4’(B3+B3’)

 B1’B2’B3’ + B1’B2’B3 + B1’B2B3’ + B1B2’B3 + B1B2’B4’ = B1’B2’(B3’+B3) +

B1’B2B3’ + B1B2’(B3+ B4’) = B1’B2 + B1’B2B3’ + B1B2’(B3+ B4’)

 B1’B2(1+B3’) + B1B2’(B3+ B4’)

 B1B2 + B1B2’(B3+B4’)  B1(B2+B2’(B3+B4’)

Mekelle Institute Of Technology Semster I : Mid Examination Page 5

 5) Design a 4 bit adder subtractor logic circuit. Show the truth table and logic diagrams clearly.

A 4 bit adder subtractor, means combinational of addition and subtraction for 4 bit values.

 Full adder/subtractor Truth Tables.

 The operations of both addition and subtraction can be performed by a one common binary
adder. Such binary circuit can be designed by adding an Ex-OR gate with each full adder as
shown in below figure. The figure below shows the 4 bit parallel binary adder/subtractor
which has two 4 bit inputs as A3A2A1A0 and B3B2B1B0.
 The mode input control line M is connected with carry input of the least significant bit of the
full adder. This control line decides the type of operation, whether addition or subtraction.
 Cascaded binary adders(4 bit)

 When M= 1, the circuit is a subtractor and when M=0, the circuit becomes adder. The Ex-OR
gate consists of two inputs to which one is connected to the B and other to input M. When M
= 0, B Ex-OR of 0 produce B. Then full adders add the B with A with carry input zero and
hence an addition operation is performed.
 When M = 1, B Ex-OR of 0 produce B complement and also carry input is 1. Hence the
complemented B inputs are added to A and 1 is added through the input carry, nothing but a
2’s complement operation. Therefore, the subtraction operation is performed.

Mekelle Institute Of Technology Semster I : Mid Examination Page 6

 What is inside Full adder now?

Mekelle Institute Of Technology Semster I : Mid Examination Page 7