Microcontrollers

8051 MICROCONTROLLER BASICS Module 1
MODULE 1
8051 MICROCONTROLLER BASICS
INSIDE THE COMPUTER
Important Terminologies
One of the most important features of a computer is how much memory it has. Bit is a binary
digit that can have the value 0 or 1. A Byte is defined as 8 bits. A nibble is a half byte, or 4 bits.
A word is two bytes, or 16 bits. The display is intended to show the relative size of these units,
they could all be composed of any combination is zeros and ones.
A Kilobyte is 210 bytes, which is 1024 bytes. The abbreviation K is often used to represent
kilobytes. e.g; some Floppy disks hold 356K of data. A megabyte, it 220 bytes, which is over 1
million bytes; it is exactly 1,048,576 bytes. A gigabytes is 230 bytes, which is over 1 billion
bytes, and terabytes is 240, which is over 1 trillion bytes. Suppose that a given computer has 16
megabytes of memory, that would be 16 X 2020, or 24 X 220, which is 224. Therefore 16
megabytes is 224 bytes.
Two types of memory commonly used in microcomputers are RAM, which stands for "random
access memory", sometimes called Read/Write memory and ROM stands for "read only
memory". RAM is used by the computer for temporary storage of programs that it is running.
That data is lost when the computer is turned OFF. RAM is sometimes called volatile memory.
ROM contains programs and information essential to operation of the computer. The information
in ROM is permanent, cannot be changed by the user, and is not lost when the power is turned
OFF. Therefore, it is called nonvolatile memory.
E&EE Department, Canara Engineering College | Compiled by: Prof. Divyesh Divakar
Internal Organization of Computers
The internal working of every computer can be broken down into three parts:
 CPU (Central Processing Unit)
 Memory
 I/O (Input / Output) devices
The function is the CPU is to execute and process information stored in memory. The function of
the I/O devices such as the keyboard and video monitor is to provide a means of communication
with the CPU. The CPU is connected to memory and I/O through strips of wire called a bus. The
bus inside a computer carries information from place to place just as a street bus carries people
from place to place. In every computer, there are three types of buses:
1. Address Bus
2. Data Bus
3. Control Bus
For a device, memory or I/O to be recognized by the CPU, it must be assigned an address. The
address assigned to a given device must be unique; no two devices are allowed to have the same
address. The CPU puts the address in binary, on the address bus, and the decoding circuitry finds
the device. Then the CPU uses the data bus either to get data from that device or to send data to
it. The control buses are used to provide read or write signals to the device to indicate if the CPU
is asking for information or sending information. Of the three buses, the address bus and data bus
determine the capability of a given CPU.
Data Bus and Address Bus in Computers
The address bus is used to identify the devices and memory connected to the CPU, the more
address buses available, the larger the number of devices that can be addressed. The number of
address buses for a CPU determines the number of locations with which it can communicate. The
number of locations is always equal to 2x, where x is the number of address lines, regardless of
the size of the data bus. A CPU with 16 address lines can provide a total of 65,536 (2 16) or 64K
of addressable memory. Each location can have a maximum of 1 byte of data. This is because all
general-purpose microprocessor CPU's are what is called byte addressable. The IBM PC AT uses
a CPU with 24 address lines and 16 data lines. In this case, the total accessible memory is 16
megabytes, 224 = 16 megabytes. There would be 224locations, as each location is 1 byte, there
would be 16 megabytes of memory. The address bus is a unidirectional bus, which means that
the CPU uses the address bus only to send out addresses. To summarize, the total number of
memory locations addressable by a given CPU is always equal to 2x, where x is the number of
address bits, regardless of the size of the data bus.
CPU, RAM and ROM in Computers
For the CPU to process information, the data must be stored in RAM or ROM. The function of
ROM in computers is to provide information that is fixed and permanent. This is information
such as tables for characters patterns to be displayed on the video monitor, or programs that are
essential to the working of the computer, such as programs for testing and finding the total
amount of RAM installed on the system, or for displaying information that can change with time,
such as various versions of the operating system and application packages such as work
processing or tax calculation packages. These programs are loaded from the hard device into
RAM to be processed by the CPU. The CPU cannot get the information from the disk directly
because the disk is too slow. The CPU first seeks the information to be processed from RAM or
ROM. Only if the data is not there does the CPU seek it from a mass storage device such as disk,
and then it transfers the information to RAM. For this reason, RAM and ROM are sometimes
referred to as primary memory and disks are called secondary memory.
Internal Block Diagram of CPU
A program stored in memory provides instructions to the CPU to perform an action. The action
can simply be adding data such as payroll data or controlling a machine such as a robot. The
function of the CPU is to fetch these instructions from memory and execute them. To perform
the actions of fetch and execute, all CPU's are equipped with resources such as the following:
1. Foremost among the resources at the disposal of the CPU are a number of registers. The
CPU used registers to store information temporarily. The information could be two
values to be processed, or the address of the value needed to be fetched from memory.
Registers inside the CPU can be 8-bit, 16-bit, 32-bit or even 64-bit registers, depending
on the CPU. In general, the more and bigger the registers, the better the CPU. The
disadvantage of more and bigger registers is the increased cost of such a CPU.
2. The CPU also has what is called ALU (Arithmetic Logic Unit). The ALU section of the
CPU is responsible for performing arithmetic functions such as Addition, Subtract,
Multiply and Divide, and logic functions such as AND, OR, and NOT.
3. Every CPU has what is called a program counter. The function of the program counter is
to point to the address of the next instruction to be executed. As each instruction is
executed, the program counter is incremented to point to the address of the next
instruction to executed. The contents of the program counter are placed on the address
bus to find and fetch the desired instruction. In the IBM PC, the program counter is a
register called IP, or the instruction pointer.
4. The function of the instruction decoder is to interpret the instruction fetched into the
CPU. One can think of the instruction decoder as a kind of dictionary, storing the
meaning of each instruction and what steps the CPU should take upon receiving a given
instruction. Just as a dictionary requires more pages, the more words it defines, a CPU
capable of understanding more instructions required more transistors to design.
Internal Working of Computers
A step-by-step analysis of the process a CPU would go through to add three numbers is
demonstrated below. Assume an imaginary CPU has registers called A, B. C, and D. It has an 8
bit of data bus and a 16 bit of address bus. Therefore, the CPU can access memory from
addresses 0000 to FFFFH (for a total of 10000H locations). The action to be performed by the
CPU is to put hexadecimal value 21 into register A, and then add to register A values 42H and
12H. Assume that the code for the CPU to move a value to register A is 1011 0000 (B0H) and
the code for adding a value to register A is 0000 0100 (04H). The steps to perform them are
demonstrated below.
If the program to perform the actions listed above is stored in memory locations starting at
1400H, the following would represent the contents for each memory address location.
The actions performed by the CPU to run the program above are explained below:
1. The CPU's program counter can have a value between 0000 and FFFFH. The program
counter must be set to the value 1400H, indicating the address of the first instruction code
to be executed. After the program counter has been loaded with the address of the first
instruction, the CPU is ready to execute.
2. The CPU puts 1400H on the address bus and sends it out. The memory circuitry finds the
location while the CPU activates the READ signal, indicating to memory that it wants the
byte at location 1400H. This causes the contents of memory location 1400H, which is B0,
to be put on the data bus and brought into the CPU.
3. The CPU decodes the instruction B0 with the help of its instruction decoder dictionary.
When it finds the definition for that instruction it knows it must bring into register A of
the CPU the byte in the next memory location. It commands its controller circuitry to do
exactly that. When it brings in value 21H from memory location 1401, it makes sure tha
the doors of all registers are closed except register A. Therefore, when value 21H comes
into the CPU it will go directly into register A. After completing one instruction, the
program counter points to the address of the next instruction to be executed, which in this
case is 1402H. Address 1402 is send our on the address bus to fetch the next instruction.
4. From memory location 1402H the CPU fetches code 04H. After decoding, the CPU
knows that it must add the byte sitting at the next address (1403) to the contents of
register A. After the CPU brings the value, 42H, into register A, it provides the contents
of register A along with this value to the ALU to perform the addition. It then takes the
result of the addition from the ALU's output and puts it in register A. Meanwhile the
program counter becomes 1404H , the address of the next instruction.
5. Address 1404H is put on the address bus and the code is fetched into the CPU, decoded,
and executed. This code again is adding a value to register A. The program counter and
fetching instructions.
Now suppose that address 1403H contained value 04 instead of 42H. How would the CPU
distinguish between data 04 to be added and code 04?. Code 04 for this CPU means "move the
next values into register A". Therefore, the CPU will not try to decode the next value. It simply
moves the contents of the following memory location into register A, regardless of its value.
MICROCONTROLLERS AND EMBEDDED PROCESSORS
Microcontroller versus general-purpose microprocessor
By microprocessor is meant the general-purpose microprocessors such as Intel’s x86 family

(8086, 80286, 80386, 80486, and the Pentium) or Motorola’s 680×0 family (68000, 68010,
68020, 68030, 68040, etc.). These microprocessors contain no RAM, no ROM, and no I/O ports
on the chip itself. For this reason, they are commonly referred to as general-purpose
microprocessors.
A system designer using a general-purpose microprocessor such as the Pentium or the 68040
must add RAM, ROM, I/O ports, and timers externally to make them functional. Although the
addition of external RAM, ROM, and I/O ports makes these systems bulkier and much more
expensive, they have the advantage of versatility such that the designer can decide on the amount
of RAM, ROM, and I/O ports needed to fit the task at hand. This is not the case with
microcontrollers. A microcontroller has a CPU (a microprocessor) in addition to a fixed amount
of RAM, ROM, I/O ports, and a timer all on a single chip. In other words, the processor, RAM,
ROM, I/O ports, and timer are all embedded together on one chip; therefore, the designer cannot
add any external memory, I/O, or timer to it. The fixed amount of on-chip ROM, RAM, and
number of I/O ports in microcontrollers makes them ideal for many applications in which cost
and space are critical.
In many applications, for example a TV remote control, there is no need for the computing
power of a 486 or even an 8086 microprocessor. In many applications, the space it takes, the
power it consumes, and the price per unit are much more critical considerations than the
computing power. These applications most often require some I/O operations to read signals and
turn on and off certain bits.
Microprocessor Vs Microcontroller
Microprocessor Microcontroller
 It is an IC which has only CPU inside.  It has a CPU, in addition with a fixed
They don’t have RAM, ROM and other amount of RAM, ROM and other
peripherals on chip peripherals embedded on a single chip.
 Finds applications where tasks are  It is designed to perform specific tasks
unspecific like developing software, where the relationship between the
games, websites etc input and output is defined such as
keyboards, washing machine, remotes,
mobiles, digicam, pendriveetc
 They need high amount of resources  Small amount of resources like RAM,
like RAM, ROM, I/O ports. ROM, I/O ports and hence they are
embedded on a chip. This in turn
reduces the size and the cost.

 The clock speed of the microprocessor  They operate at few MHz to 30-50
is quite high. They can operate at 1 MHZ.
GHz and above
 Do not have inbuilt serial ports  They have inbuilt serial ports
 Program and data are stored in the same  Separate memory to store program and
memory data
 Less multifunction pins on IC  Many multifunction pins on IC
 Boolean operations are not possible  Boolean operations are possible
directly. directly
 It takes many instructions to read and  It takes few instructions to read and
write data from external memory. They write data.They have one or two
have many operational codes for operational codes for moving data.
moving data from external memory to
CPU.
 It fails to offer software protection  It provides software protection
 It finds usage in higher end industrial  It finds usage in lower end industrial
projects. projects.
 It has one or two bit handling  It has many bit handling instructions
instructions
 Rapid movement of data or code from  Rapid movement of bits within the chip
external address to chip
 Eg. 8051, PIC microcontrollers
 Eg. 8085, 8086, Pentium processors
Microcontrollers for embedded systems
In the literature discussing microprocessors, we often see the term embedded

system. Microprocessors and microcontrollers are widely used in embedded system products. An
embedded product uses a microprocessor (or microcontroller) to do one task and one task only.
A printer is an example of embedded system since the processor inside it performs only one task
; namely, getting the data and printing it. Contrast this with a Pentium-based PC (or any x86
IBM-compatible PC). A PC can be used for any number of applications such as word processor,
print server, bank teller terminal, video game player, network server, or internet terminal.
Software for a variety of applications can be loaded and run. Of course the reason a PC can
perform myriad tasks is that it has RAM memory and an operating system that loads the
application software into RAM and lets the CPU run it. In an embedded system, there is only one
application software that is typically burned into ROM. An x86 PC contains or is connected to
various embedded products such as the keyboard, printer, modem, disk controller, sound card,
CD-ROM driver, mouse, and so on. Each one of these peripherals has a microcontroller inside it
that performs only one task. For example, inside every mouse there is a microcontroller that
performs the task of finding the mouse position and sending it to the PC.
Choosing a microcontroller
There are four major 8-bit microcontrollers. They are: Freescale’s 6811, Intel’s 8051, Zilog’s Z8,
and PIC 16X from Microchip Technology. Each of these microcontrollers has a unique
instruction set and register set; therefore, they are not compatible with each other. Programs
written for one will not run on the others. There are also 16-bit and 32-bit microcontrollers made
by various chip makers. With all these different microcontrollers, what criteria do designers
consider in choosing one? Three criteria in choosing microcontrollers are as follows: (1) meeting
the computing needs of the task at hand efficiently and cost effectively, (2) availability of
software development tools such as compilers, assemblers, and debuggers, and (3) wide
availability and reliable sources of the microcontroller. Next we elaborate further on each of the
above criteria.
i. The first and foremost criterion in choosing a microcontroller is that it must

meet the task at hand efficiently and cost effectively. In analyzing the needs
of a microcontroller-based project, we must first see whether an 8-bit, 16-bit,
or 32-bit microcontroller can best handle the computing needs of the task most
effectively. Among other considerations in this category are:
 Speed: What is the highest speed that the microcontroller supports?
 Packaging: Does it come in a 40-pin DIP (dual inline package) or a QFP

(quad flat package), or some other packaging format? This is important in
terms of space, assembling, and prototyping the end product.
 Power consumption: This is especially critical for battery-powered products.
 The amount of RAM and ROM on chip.
 The number of I/O pins and the timer on the chip.
 How easy it is to upgrade to higher-performance or lower power-consumption versions.
 Cost per unit: This is important in terms of the final cost of the product in
which a microcontroller is used. For example, there are microcontrollers
that cost 50 cents per unit when purchased 100,000 units at a time.
ii. The second criterion in choosing a microcontroller is how easy it is to develop products
around it. Key considerations include the availability of an assembler, debugger, a code-
efficient C language compiler, emulator, technical support, and both in-house and outside
expertise. In many cases, third-party vendor (that is, a supplier other than the chip
manufacturer) support for the chip is as good as, if not better than, support from the chip
manufacturer.
iii. The third criterion in choosing a microcontroller is its ready availability in
needed quantities both now and in the future. For some designers this is even
more important than the first two criteria. Currently, of the leading 8-bit
microcontrollers, the 8051 family has the largest number of diversified (multiple source)
suppliers. By supplier is meant a producer besides the originator
of the microcontroller. In the case of the 8051, which was originated by Intel,
several companies also currently produce (or have produced in the past) the
8051. These companies include: Intel, Atmel, Philips/Signetics, AMD,
Infineon (formerly Siemens), Matra, and Dallas Semiconductor.
8051 MICROCONTROLLER ARCHITECTURE
The 8051 Microcontroller architecture block diagram is as shown below
The 8051 architecture consists of these specific features:
 Eight-bit CPU with registers A (the accumulator) and B, Sixteen-bit program counter
(PC) and data pointer (DPTR), Eight-bit program status word (PSW)
 Eight-bit stack pointer (SP)

 Internal ROM or EPROM (8751) , (8031) to 4K (8051) Internal RAM of 128
bytes(SFR)
 Four register banks, each containing eight registers. Sixteen bytes, which may be
addressed at the bit level Eighty bytes of general-purpose data memory
 Thirty-two input/output pins arranged as four 8-bit ports: P0-P3
 Two 16-bit timer/counters: T0 and T1
 Full duplex serial data receiver/transmitter: SBUF
 Control registers: TCON, TMOD, SCON, PCON, IP, and IE Two external and three
internal interrupt sources
 Oscillator and clock circuits
The 8051 block diagram is as shown below
PIN DESCRIPTION
Note: Alternate functions are shown below the port name (in parenthesis). Pin numbers and pin
names are shown inside the DIP package.
Pins 1-8: Port 1- Each of these pins can be configured as an input or an output.
Pin 9: RST- A logic one on this pin disables the microcontroller and clears the contents of most
registers. In other words, the positive voltage on this pin resets the microcontroller. By applying
logic zero to this pin, the program starts execution from the beginning.
Pins10-17: Port 3-Similar to port 1, each of these pins can serve as general input or output.
Besides, all of them have alternative functions:
Pin 10: RXD- Serial asynchronous communication input or Serial synchronous communication
output.
Pin 11: TXD-Serial asynchronous communication output or Serial synchronous communication

clock output.
Pin 12: INT0- Interrupt 0 input.
Pin 13:INT1- Interrupt 1 input.
Pin 14:T0- Counter 0 clock input.
Pin 15:T1 -Counter 1 clock input.
Pin 16: WR- Write to external (additional) RAM.
Pin 17: RD- Read from external RAM.
Pins 18, 19: X2, X1- Internal oscillator input and output. A quartz crystal which specifies
operating frequency is usually connected to these pins. Instead of it, miniature ceramics
resonators can also be used for frequency stability.
Pin 20: GND- Ground.
Pins 21-28: Port 2- If there is no intention to use external memory then these port pins are
configured as general inputs/outputs. In case external memory is used, the higher address byte,
i.e. addresses A8-A15 will appear on this port. Even though memory with capacity of 64Kb is
not used, which means that not all eight port bits are used for its addressing, the rest of them are
not available as inputs/outputs.
Pin 29:PSEN- If external ROM is used for storing program then a logic zero (0) appears on it
every time the microcontroller reads a byte from memory.
Pin 30: ALE- Prior to reading from external memory, the microcontroller puts the lower address
byte (A0-A7) on P0 and activates the ALE output. After receiving signal from the ALE pin, the
external register (usually 74HCT373 or 74HCT375 add-on chip) memorizes the state of P0 and
uses it as a memory chip address. Immediately after that, the ALU pin is returned its previous
logic state and P0 is now used as a Data Bus. As seen, port data multiplexing is performed by
means of only one additional (and cheap) integrated circuit. In other words, this port is used for
both data and address transmission.
Pin 31: EA- By applying logic zero to this pin, P2 and P3 are used for data and address
transmission with no regard to whether there is internal memory or not. It means that even there
is a program written to the microcontroller, it will not be executed. Instead, the program written
to external ROM will be executed. By applying logic one to the EA pin, the microcontroller will
use both memories, first internal then external (if exists).
Pins 32-39: Port 0- Similar to P2, if external memory is not used, these pins can be used as
general inputs/outputs. Otherwise, P0 is configured as address output (A0-A7) when the ALE pin
is driven high (1) or as data output (Data Bus) when the ALE pin is driven low (0).
Pin 40: VCC- +5V power supply.
The 8051 Oscillator and Clock
The heart ofthe 8051 is the circuitry that generates the clock pulses by which all internal operations
are synchronized. Pins XTAL1 and XTAL2 are provided for connecting a resonant network to
form an oscillator. Typically, a quartz crystal and capacitors are employed, as shown in Figure.
The crystal frequency is the basic internal clock frequency of the microcontroller. The oscillator
formed by the crystal, capacitors, and an on-chip inverter generates a pulse train at the frequency of
the crystal, as shown in Figure.
The clock frequency, f, establishes the smallest interval of time within the micro-controller,
called the pulse, P, time. T state is defined as one subdivision of the operation performed in
one clock period.The smallest interval of time to accomplish any simple instruction, or part of a
complex instruction, however, is the machine cycle. The machine cycle is itself made up of six
states. A state is the basic time interval for discrete operations of the microcontroller such as
fetching an opcode byte, decoding an opcode, executing an opcode, or writing a data byte. Two
oscillator pulses define each state.
Program instructions may require one, two, or four machine cycles to be executed, depending on
the type of instruction. Instructions are fetched and executed by the micro-controller automatically,
beginning with the instruction located at ROM memory address 0000h at the time the
microcontroller is first reset. Time required for completing the execution of an instruction is
called an instruction cycle. For example: MOV A,#25h is a 1 machine cycle instruction, MOV
60h,40h is a 2 machine cycle instruction and MUL AB is a 4 machine cycle instruction.
To calculate the time any particular instruction will take to be executed, find the number of
cycles, C. The time to execute that instruction is then found by multiplying C by 12 and dividing
the product by the crystal frequency: Tinst = C x 12d / crystal frequency
For example, if the crystal frequency is 16 megahertz, then the time to execute an ADD A, R1
one-cycle instruction is .75 microseconds.
Registers:
In the CPU, registers are used to store information temporarily. This information could be a byte of
data to be processed or an address pointing to the data to be fetched.
A and B CPU Registers
The 8051 contains 34 general-purpose, or working, registers. Two of these, registers A and B,
comprise the mathematical core of the 8051 central processing unit (CPU). The A (accumulator)
register is the most versatile of the two CPU registers and is used for many operations,
including addition, subtraction, integer multiplication and division, and Boolean bit
manipulations. The A register is also used for all data transfers between the 8051 and any
external memory. The B register is used with the A register for multiplication and division
operations and has no other function other than as a location where data may be stored.
The other 32 are arranged as part of internal RAM in four banks, B0-B3, of eight registers each,
named R0 to R7.
INTERNAL RAM
The 128-byte internal RAM, is organized into three distinct areas:
1. Thirty-two bytes from address 00h to IFh that make up 32 working registers or-
ganized as four banks of eight registers each. The four register banks are numbered 0 to
3 and are made up of eight registers named R0 to R7. Each register can be addressed by
name (when its bank is selected) or by its RAM address. Thus R0 of bank 3 is R0 (if
bank 3 is currently selected) or address I8h (whether bank 3 is selected or not). Bits RS0
and RS1 in the PSW determine which bank of registers is currently in use at any time
when the program is running. Register banks not selected can be used as general-
purpose RAM. Bank 0 is selected upon reset.
2. A bit-addressable area of 16 bytes occupies RAM byte addresses 20h to 2Fh, forming
a total of 128 addressable bits. An addressable bit may be specified by its bit address
of 00h to 7Fh, or 8 bits may form any byte address from 20h to 2Fh. Thus, for
example, bit address 4Fh is also bit 7 of byte address 29h. Addressable bits are useful
when the program need only remember a binary event (switch on, light off, etc.).
3. A general-purpose RAM area above the bit area, from 30h to 7Fh, addressable as
bytes.
7F
Scratch Pad RAM

30
2F
Bit-Addressable RAM
20
1F R7 Register Bank 3
18 R0
17 R7
Register Bank 2
10 R0
0F R7 Register Bank 1
08 R0
07 R7
Register Bank 0
00 R0
Program Counter and Data Pointer
The 8051 contains two 16-bit registers: the program counter (PC) and the data pointer (DPTR).
Each is used to hold the address of a byte in memory. The program counter points to the address of
the next instruction to be executed. As CPU fetches the opcode from the program ROM, the
program counter is incremented to point to the next instruction.When 8051 is powered up, PC has
the value of 0000h. The first opcode must be burned into memory location 0000h
Program instruction bytes are fetched from locations in memory that are addressed by the PC.
Program ROM may be on the chip at addresses 0000h to 0FFFh, external to the chip for addresses
that exceed 0FFFh, or totally external for all addresses from 0000h to FFFFh. The PC is
automatically incremented after every instruction byte is fetched and may also be altered by certain
instructions. The PC is the only register that does not have an internal address.
The DPTR register is made up of two 8-bit registers, named DPH and DPL, that are used to furnish
memory addresses for internal and external code access and external dataaccess. The DPTR is under
the control of program instructions and can be specified by its 16-bit name, DPTR, or by each
individual byte name, DPH and DPL. DPTR does not have a single internal address; DPH and
DPL are each assigned an address.
DPTR DPH DPL
PC PC(Program Counter
The Stack and the Stack Pointer
The stack is a section of RAM used by the CPU to store information temporarily. This
information could be data or an address. The Register used to access the stack is called
Stack Pointer(SP). The 8-bit stack pointer (SP) register is used by the 8051 to hold an internal
RAM address that is called the "top of the stack." The address held in the SP register is the
location in internal RAM where the last byte of data was stored by a stack operation. When
8051 is powered up, the SP register contains value 07 which means 08 is the first location
used for stack by the 8051.When data is to be placed on the stack, the SP increments before
storing data on the stack so that the stack grows up as data is stored. As data is retrieved
from the stack, the byte is read from the stack, and then the SP decrements to point to the next
available byte of stored data. The stack operation is as shown below
The stack is limited in height to the sizeoftheinternalRAM. The stack has the potentialto overwrite
valuable data in theregister banks, bit-addressableRAM, and scratch-padR AM areas.
The stack is normally placed high in internal RAM, by an appropriate choice of the number
placed in the SP register, to avoid conflict with the register, bit, and scratch-pad internal R A M
areas.
Flags and the Program Status Word (PSW)
Flags are 1-bit registers provided to store the results of certain program instructions. Other
instructions can test the condition of the flags and make decisions based upon the flag states. In
order that the flags may be conveniently addressed, they are grouped inside the program status
word (PSW) and the power control (PCON) registers.
The 8051 has four math flags that respond automatically to the outcomes of math operations
and three general-purpose user flags that can be set to 1 or cleared to 0 by the programmer as
desired. The math flags include carry (CY), auxiliary carry (AC), overflow (OV), and parity
(P). User flags are named F0, GF0, and GF1; they are general-purpose flags that may be used
by the programmer to record some event in the program. Note that all of the flags can be set
and cleared by the programmer at will. The math flags, however, are also affected by math
operations.
The PSW contains the math flags, user program flag F0, and the register select bits that
identify which of the four general-purpose register banks is currently in use by the program.
The program status word Register is shown in Figure.
CY, Carry flag:-This flag is set whenever there is a carry out from D7 bit. This flag is affected
after an 8-bit addition or subtraction. It can also be set to 1 or 0 directly by an instruction such
as “SETB C”(set bit carry) and “CLR C” (clear carry). This flag is used to detect errors in
unsigned arithmetic operations.
AC,the auxiliary carry flag:- If there is a carry from D3 to D4 during an ADD or SUB
operation, this bit is set otherwise cleared.
P,the parity flag:-The parity flag reflects the number of 1s in the A register only. If A register
contains an odd number of 1s, then P=1 otherwise P=0.
OV, the overflow flag:-This flag is set whenever the result of a signed number is too large,
causing the higher order bit to overflow into the sign bit. This flag is used to detect errors in
signed arithmetic operations.
SPECIAL FUNCTION REGISTERS

The 8051 operations that do not use the internal 128-byte RAM addresses from 00h to 7Fh are
done by a group of specific internal registers, each called a special-function register (SFR),
which may be addressed much like internal RAM, using addresses from 80h to FFh.
Some SFRs are also bit addressable, as is the case for the bit area of RAM. This feature allows
the programmer to change only what needs to be altered, leaving the remaining bits in that SFR
unchanged.
Not all of the addresses from 80h to FFh are used for SFRs, and attempting to use an address that
is not defined, or "empty," results in unpredictable results The SFR names and equivalent
internal RAM addresses are given in the following table:
Internal RAM Bit
Name Function Address (Hex) Addressable
A Accumulator 0E0 Y
B Arithmetic 0F0 Y
DPH Addressing external memory 83
DPL Addressing external memory 82
IE Interrupt enable control 0A8 Y
IP Interrupt priority 0B8 Y
P0 Input/output port latch 80 Y
P1 Input/output port latch 90 Y
P2 Input/output port latch A0 Y
P3 Input/output port latch 0B0 Y
PCON Power control 87
PSW Program status word 0D0 Y
SCON Serial port control 98 Y
SBUF Serial port data buffer 99
SP Stack pointer 81
TMOD Timer/counter mode control 89
TCON Timer/counter control 88 Y
TL0 Timer 0 low byte 8A
TH0 Timer 0 high byte 8C
TL1 Timer 1 low byte 8B
TH1 Timer 1 high b y t e 8D
Note that the PC is not part of the SFR and has no internal RAM address.
SFRs are named in certain opcodes by their functional names, such as A or TH0,
andarereferenced by other opcodes by their addresses, such as 0E0h or 8Ch. Note that any
address used in the program must start with a number; thus address E0h for the A SFR begins
with 0. Failure to use this number convention will result in an assembler error when the
program is assembled.
Internal ROM
The 8051 is organized so that data memory and program code memory can be in two entirely
different physical memory entities. Each has the same address ranges.
A corresponding block of internal program code, contained in an internal ROM, occupies code
address space 0000h to 0FFFh. The PC is ordinarily used to address program code bytes from
addresses 0000h to FFFFh. Program addresses higher than 0FFFh, which exceed the internal
ROM capacity, will cause the 8051 to automatically fetch code bytes from external program
memory. Code bytes can also be fetched exclusively from an external memory, addresses
0000h to FFFFh, by connecting the external access pin (EA pin 31 on the DIP) to ground. The
PC does not care where the code is; the circuit designer decides whether the code is found
totally in internal ROM, totally in external ROM, or in a combination of internal and external
ROM.
MEMORY ADDRESS DECODING
The CPU provides the address of the data desired, but it is the job of the decoding
circuitry to locate the selected memory block. To explore the concept of decoding
circuitry, we look at various methods used in decoding the addresses. In this discussion we
use SRAM or ROM for the sake of simplicity.Memory chips have one or more pins called
CS (chip select), which must be activated for the memory’s contents to be accessed.
As can be seen from the data sheets of SRAM and ROM, the CS input of a memory chip is
normally active low and is activated by the output of the memory decoder. Normally
memories are divided into blocks, and the output of the decoder selects a given memory
block. There are three ways to generate a memory block selector: (a) using simple logic
gates, (b) using the 74LS138, or (c) using programmable logics. Each method is described
below with some examples.
(a) Using simple logic gates:
The simplest method of constructing decoding circuitry is the use of a NAND gate. The
output of a NAND gate is active low, and the CS pin is also active low, which makes them
a perfect match. In cases where the CS input is active high, an AND gate must be used.
Using a combination of NAND gates and inverters, one can decode any address range. An
example of this is shown in figure, which shows that A15 – A12 must be 0011 in order to
select, the chip. This results in the assignment of addresses 3000H to 3FFFH to this
memory chip.
(b) Using the 74LS138:
This is one of the most widely used address decoders. The 3 inputs A, B, ’and C generate 8
active-low outputs YO – Y7. Each Y output is connected to CS of a memory chip,
allowing control of 8 memory blocks by a single 74LS138. In the 74LS138, where A, B,
and C select which output is activated, there are three additional inputs, G2A, G2B, and
Gl. G2A and G2B are both active low, and Gl is active high.
If any one of the inputs Gl, G2A, or G2B is not connected to an address signal (s ometimes
they are connected to a control signal), they must be activated permanently either by
Vcc or ground, depending on the activation level. Example 14-6 shows the design and the
address range calculation for the 74LS138 decoder.
(c) Using programmable logics:
Other widely used decoders are programmable logic chips such as PAL and GAL chips.
One disadvantage of these chips is that they require PAL/GAL software and a burner
(programmer), whereas the 74LS138 needs neither of these. The advantage of these chips
is that they can be programmed for any combination of address ranges, and so are much
more versatile. This plus the fact that PALs and GALs have 10 or more inputs (in contrast
to 6 in the 74138) means that they can accommodate more address inputs.
8031/51 INTERFACING WITH EXTERNAL ROM AND RAM
The system designer is not limited by the amount of internal RAM and ROM available on chip.
Two separate external memory spaces are made available by the 16-bit PC and DPTR and by
different control pins for enabling external ROM and RAM chips. Internal control circuitry
accesses the correct physical memory, depending upon the machine cycle state and the opcode
being executed.
There are several reasons for adding external memory, particularly program memory, when
applying the 8051 in a system. The manufacturers make available an EPROM version, the 8751,
which has 4K of on-chip EPROM that may be programmed and erased as needed as the program is
developed. The resulting circuit board layout will be identical to one that uses a factory-programmed
8051. The only drawbacks to the 8751are the specialized EPROM programmers that must be used
to program the non-standard 40-pin part, and the limit of "only" 4096 bytes of program code.
The 8751 solution works well if the program will fit into 4K bytes. Unfortunately, many times,
particularly if the program is written in a high-level language, the program size exceeds 4K bytes,
and an external program memory is needed. Again, the manufacturers provide a version for the job,
the ROMless 8031. The EA pin is grounded when using the 8031, and all program code is
contained in an external EPROM that may be as large as 64K bytes and that can be programmed
using standard EPROM programmers.
External RAM, which is accessed by the DPTR, may also be needed when 128 bytes of internal
data storage is not sufficient. External RAM, up to 64K bytes, may also be added to any chip in
the 8051 family.
Connecting External Memory
Figure shows the connections between an 8031 and an external memory configuration consisting of
16K bytes of EPROM and 8K bytes of static RAM. The 8051 accesses external RAM whenever
certain program instructions are executed. External ROM is accessed whenever the EA (external
access) pin is connected to ground or when the PC contains an address higher than the last address in
the internal 4K bytes ROM (0FFFh). 8051 designs can thus use internal and external ROM
automatically; the 8031, having no internal ROM, must have EA grounded.
Figure shows the timing associated with an external memory access cycle. During any memory
access cycle, port 0 is time multiplexed. That is, it first provides the lower byte of the 16-bit
memory address, then acts as a bidirectional data bus to write or read a byte of memory data. Port 2
provides the high byte of the memory address during the entire memory read/write cycle.
The lower address byte from port 0 must be latched into an external register to save the byte.
Address byte save is accomplished by the ALE clock pulse that provides the correct timing for the
'373 type data latch. The port 0 pins then become free to serve as a data bus.
If the memory access is for a byte of program code in the ROM, the PSEN (program store enable)
pin will go low to enable the ROM to place a byte of program code on the data bus. If the access
is for a RAM byte, the WR (write) or RD (read) pins will go low, enabling data to flow between
the RAM and the data bus.
The ROM may be expanded to 64K by using a 27512 type EPROM and connecting the remaining
port 2 upper address lines A14-A15 to the chip.
At this time the largest static RAMs available are 32K in size; RAM can be expanded to 64K by
using two 32K RAMs that are connected through address A14 of port 2.
8051 ADDRESSING MODES
Data is stored at a source address and moved (actually, the data is copied) to a destination
address. The ways by which these addresses are specified are called the addressing modes. The
8051 mnemonics are written with the destination address named first, followed by the source
address.
1. Immediate Addressing Mode
In this addressing mode, the source operand is a constant. The data source is immediately
available as part of the instruction itself. When the instruction is assembled, the operand
comes immediately after the opcode. The immediate data must be preceded by the pound sign
(#).
This addressing mode can be used to load information into any of the registers including the
DPTR register. For example
MOV A, # 25 H ; Load 25H into A
MOV R4, # 62 ; Load the decimal value 62 into R4
MOV B, # 40H ; Load the 40H into B
MOV DPTR, # 4521H ; DPTR=4512H or ( MOV DPL, # 21H , MOV DPH, # 45H)
This mode can also be used to send data to 8051 ports. For example
MOV P1, # 25 H ; Load 25H into P1
When the 8051 executes an immediate data move, the program counter is automatically
incremented to point to the byte(s) following the opcode byte in the program memory.
Whatever data is found there is copied to the destination address.
2. Register Addressing Mode
Certain register names may be used as part of the opcode mnemonic as sources or destinations
of data. Registers A, DPTR, and R0 to R7 may be named as part of the opcode mnemonic.
For example,
MOV A, R0 ; Copy the contents of R0 into A
MOV R2, A ; Copy the contents of A into R2
ADD A, R5 ; Add the contents of R5 into contents of A
MOV R7, DPL ; Copy the contents of DPL into R7

MOV R6, DPH ; Copy the contents of DPH into R6
Note: The data can be moved between the accumulator and Rn (n=0 to 7), but not between
registers.
Other registers in the 8051 may be addressed using the direct addressing mode. Some
assemblers can equate many of the direct addresses to the register name so that register names
may be used instead of register addresses. Remember that the registers used in the opcode as
R0 to R7 are the ones that are currently chosen by the bank-select bits, RS0 and RS1 in the
PSW.
3. Direct Addressing Mode
All 128 bytes of internal RAM and the SFRs may be addressed directly using the single-byte
address assigned to each RAM location and each special-function register.
In the direct addressing mode, the data is in a RAM memory location whose address is known
and this address is given as a part of the instruction. For example,
MOV R0,40H ; Save content of RAM location 40H in R0
MOV 56H,A ; Save content of A in RAM location 56H
MOV R4,7FH ; Save contents of RAM location 7FH in R4
RAM locations 0 to 7 are allocated to bank 0 registers R0-R7. These registers can be accessed in
two ways
MOV A, 04h or MOV A,R4 ;Copy R4 into A
MOV A, 07h or MOV A,R7 ;Copy R7 into A
Internal RAM uses addresses from 00 to 7Fh to address each byte.
Only one bank of working registers is active at any given time. The PSW special-function
register holds the bank-select bits, RS0 and RS1, which determine which register bank is in use.
When the 8051 is reset, RS0 and RS 1 are set to 00 to select the working registers inbank 0,
located from 00h to 07h in internal RAM.
Reset sets SP to 07h, and the stack will grow up as it is used. This growing stack will overwrite
the register banks above Bank0. Another major use of direct addressing is the stack. Only
direct addressing mode is allowed for pushing onto the stack. Pushing the accumulator onto
the stack must be coded as “PUSH 0E0H. Similarly pushing R3 of Bank0 is coded as “PUSH
03”. Direct addressing mode must be used for the POP instruction also. For example, “POP
04”, will pop the top of the stack into R4 of Bank 0.
4. Register Indirect Addressing Mode
The indirect addressing mode uses a register to hold the actual address that will finally be
used in the data move; the register itself is not the address, but rather the number in the
register. Indirect addressing for MOV opcodes uses register R0 or R1, often called "data
pointers", to hold the address of one of the data locations, which could be a RAM or an
SFR address. The number that is in the pointing register (Rp) cannot be known unless the
history of the register is known. The mnemonic symbol used for indirect addressing is the
"at" sign, which is printed as @.
The moves made possible using immediate, direct, register and indirect addressing modes are
as follows:
Mnemonic Operation
MOV @Rp,#n ;Copy the immediate byte n to the address in Rp
MOV @Rp,add ;Copy the contents of add to the address in Rp
MOV @Rp,A ;Copy the data in A to the address in Rp
MOV add,@Rp ;Copy the contents of the address in Rp to add
MOV A,@Rp ;Copy the contents of the address in Rp to A
The following table shows examples of MOV opcodes, using immediate, register, direct, and
indirect modes
Mnemonic Operation
MOV A,@R0 ;Copy the contents of the address in R0 to the A register
MOV add,@R0 ; Copy the contents of the address in R0 to add
MOV @R1,A ; Copy the contents of A to the address in R1
MOV @R0,80h ;Copy the contents of the port 0 pins to the address in RO
One of the advantages of this addressing mode is that it makes accessing data dynamic rather
than static as in the case of direct addressing mode. For example,
Loading 55H into RAM location 40H in Register indirect addressing mode is as follows
MOV A, #55H ; Load A with value 55H
MOV R0, #40H ; Load the pointer R0=40H
MOV @R0,A ; Copy A to location R0 points to
Limitation is that only registers R0, R1 are the only registers that can be used for pointers.
Since R0 and R1 are 8 bits wide, their use is limited to accessing any information in the
internal RAM (scratch pad memory of 30H-7FH or SFR).
5. Indexed addressing mode and on –chip ROM access
The external memory can be as large as 64K bytes for each of the RAM and ROM memory
areas. Opcodes that access this external memory always use indirect addressing to specify the
external memory. DPTR register can address the maximum RAM space of 0000h to FFFFh.
The instruction used for this mode is “MOVC A, @A+DPTR” The 16 bit register DPTR and
register A are used to form the address of the data element stored in on-chip ROM. In this
instruction the contents of A are added to the 16-bit register DPTR to form the 16 bit address
of the needed data. For example,
Mnemonic Operation
MOVXA,@Rp ;Copy the contents of the external address in Rp to A
MOVX A,@DPTR ;Copy the contents of the external address in DPTR to A

MOVX@Rp,A ;Copy data from A to the external address in Rp
MOVX@DPTR,A ;Copy data from A to the external address in DPTR
The following table shows examples of external moves using register and indirect addressing
modes:
Mnemonic Operation
MOVX @DPTR,A ;Copy data from A to the 16-bit address in DPTR
MOVX @R0,A ;Copy data from A to the 8-bit address in R0
Code Memory Read-Only Data Moves
Data moves between RAM locations and 8051 registers are made by using MOV and MOVX
opcodes. The data is usually of a temporary or "scratch pad" nature and disappears when the
system is powered down. There are times when access to a preprogrammed mass of data is
needed, such as when using tables of predefined bytes. This data must be permanent to be of
repeated use and is stored in the program ROM using assembler directives that store
programmed data anywhere in ROM that the programmer wishes.
Access to this data is made possible by using indirect addressing and the A register in
conjunction with either the PC or the DPTR, as shown in Figure.
In both cases, the number in register A is added to the pointing register to form the address in
ROM where the desired data is to be found. The data is then fetched from the ROM address so
formed and placed in the A register. The original data in A is lost, and the addressed data takes
its place.
As shown in the following table, the letter C is added to the MOV mnemonic to high-light the
use of the opcodes for moving data from the source address in the Code ROM to the A register
in the 8051:
Mnemonic Operation
MOV DPTR,#1234h ;Copy the immediate number 1234h to the DPTR
MOV A,#56h ;Copy the immediate number56h to A
MOVC A,@A+DPTR ; Copy the contents of address 128Ah to A
MOVC A,@A+PC ;Copies the contents of address 4059h to A if the PC contained

4000h and A contained 58h when the opcode is executed.
The PC is incremented by one (to point to the next instruction) before it is added to A to form
the final address of the code. All data is moved from the code memory to the A register
MOVC is normally used with internal or external ROM and can address 4K of internal or 64K
bytes of external code.
6. Relative addressing mode
They are used only with conditional jump instructions. The relative address is an 8 bit signed
number which is automatically added to the PC to make address of the next instruction. The 8 bit
signed value gives an address range of +127 to -127 locations.
For example: SJMP 04
8000 80 (80 is the opcode for SJMP)

8001 04 (4 is the signed value that should be added to PC)
After the execution PC=8002h+04h=8006h
The main advantage of relative addressing is that address is relative to position in the memory.
7. Absolute addressing mode
It is used only by the AJMP (absolute jump) and ACALL (absolute call) instructions. These are 2
byte instructions. The absolute addressing mode specifies the lowest 11 bit of the memory
address part of the instruction. The upper 5 bit of the destination address is the upper 5 bit of PC.
8. Long addressing mode
It is used only by the LJMP and LCALL instructions. These are 3 byte instructions. The address
specifies the full 16 bit destination address to the jump or call can be made to a location within a
64K byte code memory space.
LJMP 9000h means the PC will be loaded with 9000 after the execution of this instruction and
program execution will be transferred to 9000h
9. Bit inherent addressing mode:
In this addressing, the address of the flag which contains operand, is implied in the opcode of the
instruction.
CLR C and SETBC are the instructions.
The main feature of 8051 is that its ability to access the registers, RAM and I/O ports in bits
instead of bytes.
Single bit instructions use only Direct addressing mode
10. Bit Direct addressing mode
The RAM space 20h to 2Fh and most of the SFR are bit addressable. Bit address values between
00-7F
For example; CLR 05h ; clears bit B5 of 20h RAM location
SETB 12h ; sets the bit B2 of 22h RAM location

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8051 MICROCONTROLLER BASICS Module 1

8051 MICROCONTROLLER BASICS

INSIDE THE COMPUTER

Internal Organization of Computers

Data Bus and Address Bus in Computers

CPU, RAM and ROM in Computers

Internal Block Diagram of CPU

Internal Working of Computers

MICROCONTROLLERS AND EMBEDDED PROCESSORS

Microcontroller versus general-purpose microprocessor

By microprocessor is meant the general-purpose microprocessors such as Intel’s x86 family

reduces the size and the cost.

Microcontrollers for embedded systems

In the literature discussing microprocessors, we often see the term embedded

i. The first and foremost criterion in choosing a microcontroller is that it must

 Packaging: Does it come in a 40-pin DIP (dual inline package) or a QFP

8051 MICROCONTROLLER ARCHITECTURE

The 8051 Microcontroller architecture block diagram is as shown below

The 8051 architecture consists of these specific features:

 Eight-bit stack pointer (SP)

The 8051 block diagram is as shown below

Pin 11: TXD-Serial asynchronous communication output or Serial synchronous communication

Pin 12: INT0- Interrupt 0 input.

Pin 13:INT1- Interrupt 1 input.

Pin 14:T0- Counter 0 clock input.

Pin 15:T1 -Counter 1 clock input.

Pin 16: WR- Write to external (additional) RAM.

Pin 17: RD- Read from external RAM.

Pin 20: GND- Ground.

Pin 40: VCC- +5V power supply.

The 8051 Oscillator and Clock

A and B CPU Registers

The 128-byte internal RAM, is organized into three distinct areas:

purpose RAM. Bank 0 is selected upon reset.

Scratch Pad RAM

Program Counter and Data Pointer

DPTR DPH DPL

The Stack and the Stack Pointer

Flags and the Program Status Word (PSW)

The program status word Register is shown in Figure.

SPECIAL FUNCTION REGISTERS

MEMORY ADDRESS DECODING

(a) Using simple logic gates:

(b) Using the 74LS138:

(c) Using programmable logics:

8031/51 INTERFACING WITH EXTERNAL ROM AND RAM

Connecting External Memory

8051 ADDRESSING MODES

1. Immediate Addressing Mode

MOV A, # 25 H ; Load 25H into A

MOV R4, # 62 ; Load the decimal value 62 into R4

MOV B, # 40H ; Load the 40H into B

MOV P1, # 25 H ; Load 25H into P1

2. Register Addressing Mode

MOV A, R0 ; Copy the contents of R0 into A

MOV R2, A ; Copy the contents of A into R2

ADD A, R5 ; Add the contents of R5 into contents of A

MOV R7, DPL ; Copy the contents of DPL into R7

3. Direct Addressing Mode

MOV R0,40H ; Save content of RAM location 40H in R0

MOV 56H,A ; Save content of A in RAM location 56H

MOV R4,7FH ; Save contents of RAM location 7FH in R4

MOV A, 04h or MOV A,R4 ;Copy R4 into A

MOV A, 07h or MOV A,R7 ;Copy R7 into A