TMS320C5X ASSEMBLY

LANGUAGE
INSTRUCTIONS
ASSEMBLY LANGUAGE SYNTAX

• The C5X instruction set supports numerically intensive signal

processing operations as well as general purpose applications, such as
multiprocessing and high-speed control.
• The C5X instruction set is a superset of the C1X and C2X instruction
sets and is source-code upward compatible with both devices.
• For programming in the assembly language the C5X assembler
assumes the following assembly language syntax.
• The general syntax for source statements is as follows:
ASSEMBLY LANGUAGE SYNTAX
• They in turn follow these guidelines:
• All statements must begin with a label, a blank, an asterisk or a
semicolon.
• Labels are optional; if used, they must begin in column 1.
• Labels may be placed either before the instruction mnemonic on the
same line or on the preceding line in the first column.
• One or more blanks must separate each field. Tab characters are
equivalent to blanks.
• Comments are optional. Comments that begin in column 1 can begin
with an asterisk or a semicolon (* or ;), but comments that begin in
any other column must begin with a semicolon.
ADDRESSING MODES
• C5X processors can address 64K words of program memory and 96K
words of data memory. C5X supports the following six addressing
modes:
• Direct addressing
• Memory-mapped register addressing
• Indirect addressing
• Immediate addressing
• Dedicated-register addressing
• Circular addressing
Direct Addressing

• The data memory used with C5X processors is split into 512 pages
each of 128 words long. The data memory page pointer (DP) in ST0
holds the address of the current data memory page.
• In the direct addressing mode of C5X, only lower-order 7 bits of the
address are specified in the instruction. The upper 9 bits are taken
from the DP.
Memory-Mapped Register Addressing
• The RAM area in page 0 is used for storing some of the registers,
interrupt vector addresses and so on.
• These locations can be accessed by specifying the actual address or by
the register name, (e.g., the AR0 can either be denoted by the actual
memory location (10h) used for storing its value or by the symbol
AR0).
• Since these memory locations can be interchangeably used with the
register names, the registers corresponding to page 0 are referred to as
memory-mapped registers (MMRs).
• The memory-mapped register addressing mode operates like the direct
addressing mode, except that the 9 MSBs of the address are forced to 0
instead of being loaded with the contents of the DP.
• The following instructions operate in the memory mapped register
addressing mode. Using these instructions does not affect the contents
of the DP:
• LAMM—Load accumulator with memory-mapped register
• LMMR—Load memory-mapped register
• SAMM—Store accumulator in memory-mapped register
• SMMR—Store memory-mapped register
Immediate Addressing

• The immediate addressing mode can be used to load either a 16-bit

constant or a constant of length 13, 9 or 7.
• Accordingly it is referred to as long immediate or short immediate
addressing mode.
• This mode is indicated by the symbol #. For e.g., ADD # 56h adds 56h
to ACC. Similarly ADD # 4567h adds 4567h to ACC
Bit-Reversed Addressing

• In the bit-reversed addressing mode, INDX specifies one-half the size

of the FFT.
• The value contained in the current AR must be equal to 2n – 1, where
n is an integer, and the FFT size is 2n.
• An AR points to the physical location of a data value. When INDX is
added to the current AR, using bit-reversed addressing, addresses are
generated in a bit-reversed fashion.
 Indirect Addressing
• The ARs AR0-AR7 are used for accessing data, using indirect addressing mode.
• In the indirect addressing mode, out of the eight ARs the one which is currently
used for accessing data is denoted by the register ARP.
• The contents of ARP can be temporarily stored in the ARB register.
• The indirect addressing mode of C5X permits the AR used for the addressing to
be updated automatically either after or before the operand is fetched.
• Hence a separate instruction is not required to update the AR.
• In the indirect addressing mode, the manner in which the memory address is
computed and the manner in which the AR is altered after the instruction
depends on the instruction.
• This is indicated to the assembler by the symbols *, *+, *–,*0+ , *0–, *BR0+
and *BR0–.
• Short Immediate Addressing---In short immediate instructions, the
operand is contained within the instruction machine code.
• Long Immediate Addressing---In long immediate instructions, the
operand is contained in the second word of a 2-word instruction There
are two long immediate addressing modes: one-operand instructions
and two-operand instructions.
• Dedicated-Register Addressing---The dedicated-registered addressing
mode operates like the long immediate addressing mode, except that
the address comes from one of two special-purpose memory-mapped
registers in the CPU: the block move address register (BMAR) and the
dynamic bit manipulation register (DBMR).
• The advantage of this addressing mode is that the address of the block
of memory to be acted upon can be changed during execution of the
program.
Circular Addressing
• Many algorithms such as convolution, correlation and finite impulse
response (FIR) filters can use circular buffers in memory to implement
a sliding window, which contains the most recent data to be processed.
• The C5X supports two concurrent circular buffers operating via the
ARs. The following five memory-mapped registers control the circular
buffer operation:
• CBSR1—Circular buffer 1 start register
• CBSR2—Circular buffer 2 start register
• CBER1—Circular buffer 1 end register
• CBER2—Circular buffer 2 end register
• CBCR—Circular buffer control register
• The 8-bit CBCR enables and disables the circular buffer operation.
• To define circular buffers, the start and end addresses are loaded into
the corresponding buffer registers first; next, a value between the start
and end registers for the circular buffer is loaded into an AR.
• The corresponding circular buffer enable bit in the CBCR should be
set.
LOAD/STORE INSTRUCTIONS
 ADDITION/SUBTRACTION INSTRUCTIONS

• In the addition/subtraction instructions of C5X, one of the operand is

ACC.
• The other operand can be PREG, ACCB or the content of memory
fetched using one of the addressing modes.
• For the ADD and SUB instructions alone, the number fetched from
memory, using dma, indirect addressing and immediate addressing with
long constant, can be shifted left in the scaling shifter by 0-16 before
performing the required operation.
MOVE INSTRUCTIONS
• The data move (DMOV) instruction copies the data from one memory
location to the next higher location. It can use either direct or indirect
addressing mode.
• For e.g., DMOV 45 copies the contents of location 45h to 46h.
BLDD Instruction This instruction is used for moving data from one data memory to another. This
permits a variety of combinations for specifying the source and destination addresses. BMAR may be
used to specify either the source address or the destination address. Alternately one of the addresses may
be specified using immediate addressing and the other address may be specified using either direct or
indirect addressing.
MULTIPLICATION INSTRUCTIONS
 Shift/logical Instructions
• One of the operands for the AND, OR and XOR instructions is ACC.
• The other operand can be the content of a memory location specified
using direct addressing or indirect addressing.
• Alternately a long constant can be specified using immediate addressing.
In this case the constant may be shifted by 0–15 bits towards left before
performing the operation.
• AND ANDing the ACC with a long constant k, the content of a dma or
pma
• OR ORing the ACC with a long constant k, the content of a dma or pma
PROGRAM CONTROL INSTRUCTIONS
• The C5X instruction set has both conditional and unconditional branch
and call instructions.
• The branch and call instructions of C5X permit more than one
condition to be tested using a single instruction.
• Branching occurs only if all the conditions are satisfied. The
conditions which can be tested and the corresponding condition codes
are given
 PUSH and POP Instructions
• The PUSH instruction pushes the values down one level in the seven lower locations of
the stack.
• The contents of the accumulator low byte (ACCL) are copied to the top of the stack
(TOS).
• The values on the stack are pushed down before the ACC value is copied. The hardware
stack is last-in, first-out with eight locations
• If more than eight pushes (CALA, CALL, CC, INTR, NMI, PSHD, PUSH or TRAP
instructions) occur before a POP, the first data values written are lost with each
succeeding push.
• The PSHD instruction pushes a data memory location to the top of the stack instead of
ACC after pushing the contents of the stack one level down.
• The POP and POPD instruction does the reverse operations. POP instruction pops the top
of the stack to ACC and POPD instruction pops the top of the stack to a data memory.
• When the stack is popped, the bottom word is left unaffected and hence the bottom two
words contain the same values.
RET Instruction

• When this instruction is executed, the contents of the TOS are copied
to the program counter (PC).
• The stack is popped one level after the contents are copied.
• The RET instruction is used with the CALA, CALL and CC
instructions for subroutines.
• For the RPTB instruction, the register block repeat count register
(BRCR) determines the number of times a block of instructions is
repeatedly executed.
• It should be loaded before the RPTB instruction is used.
• The PASR and PAER registers give the starting and ending address of
the block of instructions
 PERIPHERAL CONTROL
• IN and OUT Instructions
• The IN instruction of C5X reads a 16-bit number from input port and
stores it in the data memory location.
• The OUT instruction of C5X reads a 16-bit number from data memory
and writes it onto the output port.
• Instructions Used with Interrupts
• The core of C5X consists of the following on-chip devices: serial port,
TDM serial port, timer, software programmable wait state generators,
I/O ports and divide by one clock circuit. They are controlled using
memory mapped registers