LGLite Drive & Response

LGLite + 74HC125

APPLIED DIGITAL MICROSYSTEMS PVT LTD

D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22 -)28470817, 66924483/4
Email: admltd@mtnl.net.in
YahooMessenger:admmum
 Introduction to LGLite – HC125 Tristate Control

LGLite 32 channels are a new generation three-in-one product, an Interactive

Pattern Generator, Logic Analyzer and a Frequency Counter. The combination of
Pattern Generator and Logic Analyzer is a powerful tool for designing; debugging
and automated testing of digital discrete and C/CPLD/FPGA based designs.
LGLite, which is designed, as a PC hosted instrument is an ideal tool for learning
fundamentals of Digital In-Circuit testing and test program development.

To get started learning and testing embedded I2C communication protocol we

need to understand:
1. How the I2C components – (DUT – Device under Test) on the board work
before you can figure out how to test them.
2. How the LGLite tester Drive logic (Pattern Generator) and the
Response Sensor (Logic Analyzer) will be used for the test.

The SCL is an input used to clock data into the EEProm on the rising edge of the
clock and the negative falling edge is used to clock out data from the EEProm.

We have now identified that SDA pin is bi-directional for serial data transfer. We
would be using LGLite Pattern channel to drive data into the EEProm. On receipt
of this 8 bit data, the EEProm acknowledges (ACK) the receipt by pulling the
SDA line low. We need to capture this information and this would mean the on
the 9th clock pulse the SDA pin is now an output. This would mean we need to
tristate the LGLite Pattern output and capture the SDA response on the Logic
analyzer. Note: All of this happens in real time.

Hence in addition to the SCLK and SDA waveform data we need an additional
DTC (Dynamic Tristate Control) pulse from the Pattern Generator. The
Waveform for SDA and DTC is shown above. This tristate control isolates a
single pin time slices into an input or an output. Hence to effectively use LGLite
as an Digital Test equipment we need an external three state line driver
(isolator).
ATE Pin Electronics:

ATE Pin Electronics has both PG drivers and LA Response sensors (D/R, PG/LA
in short) and always exist in pairs , so that the output of a pattern driver and the
input to a LA response sensor are always tied together. Therefore, when a D/R
pair is used to force a logic input to a bi-directional IC pin, the driver portion is
enabled (DTC enable) and its output forced to a specified state. At the same
time, the response sensor portion either can be enabled to sense that driver
output or can be instructed to ignore it. Similarly, if the D/R pair is used to check
a logic output from an IC, the driver is disconnected (DTC disable) and the
response sensor is enabled.

So, for economical reasons, each test pin does not usually have its own
dedicated driver/response sensor, but shares a few driver/response sensors with
a group of other pins. This technique is called driver/sensor multiplexing.

The LGLite is fully configurable as Pattern Generator (Drive) or Logic analyzer

(Response) in-group of 8 channels. The LGLite tester has to connect external
tristate logic to achieve dynamic Driver/Response combo. We can achieve this
using external 74HCT125 – Quad 3-state line driver.
We will be using LGLite with 74HC125 extensively to learn the fundamentals of
Digital Testing to test complex protocol based devices. Please note this
Driver/Response combo is required only for bi-directional pins.

Why Tri-State:

The 74HC125 is a quad buffer/line driver with 3-state outputs controlled by the
output enable inputs (nOE). A HIGH on nOE causes the outputs to assume a
high impedance OFF-state. Inputs include clamp diodes. The LGLite tester has
to connect external tristate logic to achieve dynamic Driver/Response combo
for every async bi-directional pin.

To implement ATE Pin electronics on LGLite we need:

1. Drivers to drive the inputs to the DUT (Device under test). == PG

2. Switching circuits to the drivers to enable signal On and OFF == DTC
3. Comparators/ Logger to capture and compare the DUT output == LA

The 74HC245 is a 3−state noninverting transceiver that is used for 2−way

asynchronous communication between data buses. The device has an active low
Output Enable pin, which is used to place the I/O ports into high impedance
states. The Direction controls data flows from A to B or from B to A.

Hence for an I2C protocol testing we need 74HC125 for connecting SDA to Drive
and Response section. While we may use 74HC245 for testing 62256 RAM
wherein all 8 bits of data bus are either inputs or outputs.

1. Tristate is often called as floating or Z state. When an output is tri-stated it

looks like high impedance to another device.
2. Requires an additional control input, typically called an Enable. The
Enable controls whether the output is a LOW or HIGH (enabled) or Tri-
Stated (disabled).
3. Tri-state outputs are used where multiple outputs share a signal or bus.

Control circuitry ensures that only one device is a bus driver at any given time
(either PG drives the SDA input or SDA output drives LA) and avoid bus conflicts.
Aim: To implement the tristate control using LGLite and 74LS125:

Our aim is to create a clock pattern and drive 74HCT125 input pin #2. The output
pin #3 will duplicate input only when DTC pin #1 is permanently low. We can use
the LGLite Pattern Generator Clock creation wizard to create both clock and DTC
signal as shown below.

The LGLite main user menu and tool bar button are shown below

The first step is to configure the LGLite as 8 channel Pattern Generator (Drive
section) and 24 channels as Logic Analyser (Response section). Hence select
the config menu option and do proper setting.
The signal definition of a digital test needs to define all of the parameters
required to generate the stimulus and response required by the DUT. This means
more than just defining the sequence of logic- 1's and logic-0's necessary to test
a digital DUT. It is also necessary to include detailed timing and voltage level
information. A functional test includes Pattern, Timing and signal levels.

Patterns:
1. The patterns contain the logic values that are required to test the DUT.
2. The pattern data must be combined with the timing information to create
the correct stimulus and measure the correct response at the DUT.
3. Each logic state needs to be able to indicate if the logic applies to stimulus
or response.
4. The pattern values need to include not only logic 1 and 0 data but also
High(H), Low(L), Tri-state(Z) and “don‟t care” (X) for outputs.

Timings:
1. Pattern supplies a list of logic to be driven-to, or compared from the DUT.
2. The timing information indicates when these happen (Drive/Response).
3. The digital functional test data must explicitly state WHEN every edge
should occur.
4. Timesets (Tsets) will have the details of the period (cycle).
5. Edgesets (Esets) will indicate format and the timing details of the edge
placements for the drive and compare data.

Defining the Operation of a DUT with a Truth Table or Wave wizard:

We now go ahead to create the Clock and DTC signal using the Pattern clock
wizard as shown below. Name the Drive channel number 1& 2 as Clock & DTC
while name the Response. Channel number 9 as Output125.
Timing Edges:

These are signal timings to control Pattern drive and LA compare circuit of the
LGLite Pin Electronics

The next step is to select the testing speed (frequency of sampling) which should
be minimum twice the frequency of I2C communication speed which is approx
100Khz. Hence set the sampling clock as 200Khz.

Go to the Waveform menu option and select clock or the clock icon on the tool
bar. The clock selection dialog box opens up as shown below:
Connections:

Connect using flying lead sets,

1. LGLite Drive Pin #01 Clock to 74HC125 Pin #02
2. LGLite Drive Pin#02 DTC to 74HC125 Pin #01
3. LGLite Response Pin#09 to 74HC125 Pin #03
4. VCC & GND

The captured waveform is shown below. Note the Tristate DTC pin#01 goes low
and the Channel 9 shows the line driver Pin#02 data on Pin#09. 74HC125 pin
#03 is pulled up by 10k resistor.

Hope this document clears how easy it is to wire and drive an tri-state TTL device
and also explains the concept behind ATE pin electronics. The LGLite channels
#1 and #2 are the Drive side logic and channel #01 drive is enabled only when
Tristate DTC channel #2 goes low. The Response of 125 pin#03 is captured by
the Logic Analyzer.