LGLite I2C ATE Training

LGLite + Load Board

APPLIED DIGITAL MICROSYSTEMS PVT LTD

D-216, ANSA INDUSTRIAL ESTATE, SAKI VIHAR ROAD,
ANDHERI EAST, MUMBAI 400 072.
Tel: (91-22 -)28470817, 66924483/4
Email: admltd@mtnl.net.in
YahooMessenger:admmum
 Introduction to LGLite ATE Script – I2C demo

LGLite 32 channels are a new generation three-in-one product, an Interactive

Pattern Generator, Logic Analyzer and a Frequency Counter. The combination of
Pattern Generator and Logic Analyzer is a powerful tool for designing; debugging
and automated testing of digital discrete and C/CPLD/FPGA based designs.
LGLite, which is designed, as a PC hosted instrument is an ideal tool for learning
fundamentals of Digital In-Circuit testing and test program development.

To get started learning and testing embedded digital components we need to

understand:
1. How the digital components – (DUT – Device under Test) on the board
work before you can figure out how to test them.
2. How the LGLite tester Drive logic (Pattern Generator) and the
Response Sensor (Logic Analyzer) will be used for the test.
3. How to use LGLite ATE Scripts for writing test programs (Protocols).

Objectives:
1. Learn to operate LGLite ATE with Load board.
2. Insert 24C512 EPROM chip into ZIF socket on Load board.
3. Use LGLite Pattern Generator to provide stimulus to EPROM chip input.
4. LGLite Logic Analyzer records response from EPROM chip output.

A Load-board has been provided and should be in front of the logic analyzer for
your use. Plug your DUT (24C512) into the Load-board ZIF socket for testing.

The first step would be to load the LGC ATE software and learn the operating
menu shown below.
The sequence of steps required to run a ATE test on a 24C512 EEPROM as a
DUT would be as follows.

The set-up file loads the required signal name fields and the clocking speed for
the DUT under test. The set-up file has been saved as 24512Read.LGC. Once
you load the file the signals used for the test with their Names would be loaded.

To see the channel names we can right click on the waveform window and a
channel name menu selects the Dialog box where in you can change the names
of individual signals.

Please note the channel names are identical to the signals named in the
datasheet of 24C512. We are going to have only two pins for EEPROM testing
and would be the SCLK and SDA. They are on channel 1 and channel 2.
Select the ATE mode by checking menu item in LGATE menu as shown below.
We configure the LGATE to be used in a single bit bi-directional data bus mode.

This configures the LGC ATE as first 8 channels as Pattern Generator and the
next 8 channels as Logic Analyser. Please note that we need Channel 1 as
SCLK the I2C clock. The channel no 2 would be SDA that drives the 24C512
input pin SDA. Note the same pin SDA would return data or acknowledge in
output mode

Hence we cannot drive the PG-SDA pin (#2) into 24C512 SDA input when the
EEPROM is in output mode. Hence this PG- SDA pin has to be tristated. This tri-
state logic is implemented using 74125 on the Load board. To control the tri-state
logic we use the third pin of the LGC ATE to control the 125. The output of 74125
#3 now drives the I2C-SDA pin.

The pin #5 SDA receives the 1Y output of 125 when EEPROM is in the input
mode and 1Y is tri-state when SDA pin of I2C is in output mode. At this point of
time we need to capture the output data using LGC logic analyser pin #9.
We now set the clock frequency to match the clock frequency of your DUT. Note,
even if your device is combinational, it still has a frequency at which the data
must be presented to the chip. Clocking can be from 50Mhz to 1Khz. The data
sheet for 24C512 specifies it to be 100Khz – 300Khz.

After configuring the PG/LA channels we then clear the PG memory by clicking
ClearMemory menu item. Now we will go ahead to load test vector (or pattern) to
stimulate your DUT. The Vector file is in plain text. The openVCTfile loads the
vector and can be seen in the waveform window.

The first channel is SCLK this is standard clocking for 24C512. Note that the
clocks are in total 9 pulses. The first 8 being data bit clocking and the 9th pulse
being the acknowledge bit to be received from the 24C512.
The channel no 2 being the data bits for 24C512 and at the same time monitor
the direction pin on channel 3 that drives the 74125 tri-state buffer which isolates
the PG-SDA from I2C-SDA pin. When channel 3 is low PG-SDA drives the
24C512 SDA pin. When channel 3 is high the I2C-SDA has data to be offered.

Now we connect the LGLite ATE pin to the DUT placed on the Load board. The
LGLite ATE has been configured as Channel 1-8 as Pattern Generator (Drive
logic) while Channel 9-16 is Logic Analyser (Sensor logic).

Attach LGLite Pattern Generator to your DUT:

Configure LG-Lite PG Channel #1 thru #8 as Pattern Generator. Using flat cable,

attach LGLite channel 1-8 to Load-board header 1-8. Connect output flying lead
wire #1 SDA from Load-board to ZIF DUT PIN #6 SCLK.

The SDA pin is bi-directional and hence we must be able to tri-state PG pins
when SDA is in output mode. Hence we use 74125 tri-state buffers. Connect
channel #2 PG-SDA pin to #2 –1A of 74125. Connect pin #3 PG-DIR to #1 of
74125, which in turn controls the output 1Y. Connect 1Y#3 of 74125 to pin 5 of
I2C SDA.
Attach Logic Analyzer to your DUT:

The pattern-generator provides stimulus to your DUT. We now need to attach the
logic analyzer cables to your DUT to monitor the output of the pattern generator
& the DUT’s response to the stimulus. Connect LGLite LA input flying lead wire
#9 from Load-board to ZIF DUT PIN #5 SDA 24C512.

Power the LGLite and Load board. The I2C cycle as shown by the 24C512 is
shown below. We now have to create a stimulus test vectors using plain English
text for loading in PG memory.

Programming the LGLite ATE using English Script symbols.

Symbol Description
#TYPLGC A LGLite ATE Vector file
#REM Comment which is not executed
#VEC XXXX Defines Vector and Vector Name
#REC A 32 bit binary record for later use
#TRC (VEC XXXX) Writes vector record in Lglite Memory

The VEC XXX

#REC XXXXXXXX XXXXXXXX XXXXXXXX XXXXX111
#REC XXXXXXXX XXXXXXXX XXXXXXXX XXXXX011

The #VEC XXXX defines a new named Vector XXXX and the associated 32
bit binary data to be written in LGLite ATE memory.

The #TRC XXXX command writes the named vector record in LGLite
memory.
I2C Communication using LGLite ATE Script:

We define the Start vector using #VEC tag and the name of the vector being
INP_I2C_START. The record #REC tag defines the bit pattern for the START
vector and we require both SCL and SDA pin to be high and SDA pin to go
low in next record with SCL remaining high. The #VEC INP_I2C_START
comprises of 3 record sequence to implement the I2C start condition. The
same is true for I2C stop condition.

The waveform sequence as shown in 24C512 data sheet.

We have now defined the Start vector and the Stop vector. We go ahead to
define all the remaining vectors required for I2C communication.

After defining all the vectors we implement the I2C Read and Write protocol
by using the above-defined vectors in a well defined sequence of vectors.
The OpenVCTFile menu item loads the above 24512Write.VCT file in LGLite
Pattern Generator memory as shown below. The fourth byte is 0x55 data.
Similarly if we load 24512Read.VCT we would see the waveform in the
memory as shown below.

Ensure that we are executing the protocol at speed of 100Khz and Press the
Go Button to capture the response of 24C512.

Please note that we have actually captured the data from 24C512 by just
running a simple LGLite ATE script based protocol.

Hope this document clears the use of LGLite ATE and script programming for
testing I2C devices.