NAME: ABU MINHAJ FAROOQI

REG#: 37560
COURSE: FPGA
FINAL EXAM

ANSWER OF QUESTION 1:
B)
ANSWER OF QUESTION 2:
A)
module Reg4(I, Q, Clk, Rst);
input [3:0] I;
output [3:0] Q;
wire [3:0] Q;
input Clk, Rst;
always @(Clk) begin
if (Rst == 1 )
Q <= 4'b0000;
else
Q <= I;
end
Endmodule

B)
C)
module priority_encoder_8x3 (d_in,d_out)
input [7:0] Y;
output [2:0] d;
assign d_out
always @ (Y)
begin
8’b00000000: d = 3’b000;
8’b10000000: d = 3’b001;
8’bX1000000: d = 3’b010;
8’bXX100000: d = 3’b011;
8’bXXX10000: d = 3’b100;
8’bXXXX1000: d = 3’b101;
8’bXXXXX100: d = 3’b110;
8’bXXXXXX10: d = 3’b111; 3’XXX;
end
endmodule

ANSWER OF QUESTION 3:
A) testbench.v
module main;
reg [3:0] a1,b1;
wire [3:0] d1;
reg c,s,r1;
wire r2;
mult mult1 (c,r1,s,r2,a1,b1,d1);
initial begin forever begin c<=1'b0;
#5 c<=1'b1;
#5 c<=1'b0;
end end initial begin a1<=4'b0101;
b1<=4'b0011;
s<=1'b1;
r1<=1'b0;
end endmodule
In the theory of computation, a Moore machine is a finite-state machine whose output values are
determined only by its current state.

input clock;
// clock signal input reset;
// reset input input sequence_in;
t output reg detector_out;
parameter Zero=3'b000,
One=3'b001,
// "One" State OneZero=3'b011,

// "OneZero" State OneZeroOne=3'b010,

// "OnceZeroOne" State OneZeroOneOne=3'b110;
// "OneZeroOneOne" State reg [2:0] current_state, next_state;
// current state and next state always @(posedge clock, posedge reset) begin if(reset==1)
current_state <= Zero;
else current_state <= next_state;
end always @(current_state,sequence_in) begin case(current_state) Zero:begin
if(sequence_in==1) next_state = One;
else next_state = Zero;
end One:begin if(sequence_in==0) next_state = OneZero;
else next_state = One;
end OneZero:begin if(sequence_in==0) next_state = Zero;
else next_state = OneZeroOne;
end OneZeroOne:begin if(sequence_in==0) next_state = OneZero;
else next_state = OneZeroOneOne;
end OneZeroOneOne:begin if(sequence_in==0) next_state = OneZero;
else next_state = One;
end default:next_state = Zero;
endcase end always @(current_state) begin case(current_state) Zero: detector_out = 0;
One: detector_out = 0;
OneZero: detector_out = 0;
OneZeroOne: detector_out = 0;
OneZeroOneOne: detector_out = 1;
default: detector_out = 0;
endcase end module reg4 (clk,LD,reset,Din,Dout);
input clk,LD,reset;
input [3:0] Din;
output [3:0] Dout;
reg [3:0] Dout;
always@(posedge clk) begin if (reset == 0 & LD == 1) Dout <= Din;
end always @(posedge reset) begin Dout <= 4'b0;
end endmodule

B) A tri-state buffer is a logic inverter or a non-inverting buffer with a tri-state output stage. ...
When the enable line is not activated the buffer output stage has a high output impedance and
transmission of data is prevented.
The main use of tri-state gates is in driving logic lines or the connectors in a data bus (a
contraction of the older term ‘bus-bar’ meaning a conductor providing a voltage or current, often
from a power source, to many other devices).
The four possible configurations are shown in Figure:
Tri-state buffers (a) Inverting, active high enable with truth table (b) Non-inverting, active high
enable (c) Inverting, active low enable (d) Non-inverting, active low enable.
The input denoted E can be regarded as an enable line, which may require either an active low or
active high input signal, and when activated it will allow the gate to output either the true or
inverted data. When the enable line is not activated the buffer output stage has a high output
impedance and transmission of data is prevented.
HDLs use z to indicate a floating value, z is particularly useful for describing a tristate buffer,
whose output floats when the enable is 0.If the buffer is enabled, the output is the same as the
input. If the buffer is disabled, the output is assigned a floating value (z).
Similarly, HDLs use x to indicate an invalid logic level. If a bus is simultaneously driven to 0
and 1 by two enabled tristate buffers (or other gates), the result is x, indicating contention. If all
the tristate buffers driving a bus are simultaneously OFF, the bus will float, indicated by z.
At the start of simulation, state nodes such as flip-flop outputs are initialized to an unknown state
(x in SystemVerilog and u in VHDL). This is helpful to track errors caused by forgetting to reset
a flip-flop before its output is used.
Tristate Buffer
System Verilog
module tristate(input logic [3:0] a,
input logic en,
output tri [3:0] y);
assign y = en ? a : 4'bz;
Endmodule

VHDL

library IEEE; use IEEE.STD_LOGIC_1164.all;

entity tristate is
port(a: in STD_LOGIC_VECTOR(3 downto 0);
en: in STD_LOGIC;
y: out STD_LOGIC_VECTOR(3 downto 0));
end;
architecture synth of tristate is
begin
y <= a when en else “ZZZZ”;
end;
ANSWER OF QUESTION 4:
A)
module regFile( Ip1,
sel_i1,
Op1,
sel_o1,
Op2,
sel_o2,
RD,
WR,
rst,
EN,
clk
);
input [31:0] Ip1;
input [3:0] sel_i1,
sel_o1,
sel_o2;
input RD,
WR;
input EN,
clk,
rst;
output [31:0] Op1,
Op2;
reg [31:0] Op1,
Op2;
reg [31:0] regFile [0:15];
integer i;
wire sen;
assign sen = clk || rst;
always @ (posedge sen)
begin
if (EN == 1)
begin
if (rst == 1) //If at reset
begin
for (i = 0; i < 16; i = i + 1) begin
regFile [i] = 32'h0;
end
Op1 = 32'hx;
end
else if (rst == 0) //If not at reset
begin
case ({RD,WR})
2'b00: begin
end
2'b01: begin //If Write only
regFile [sel_i1] = Ip1;
end
2'b10: begin //If Read only
Op1 = regFile [sel_o1];
Op2 = regFile [sel_o2];
end
2'b11: begin //If both active
Op1 = regFile [sel_o1];
Op2 = regFile [sel_o2];
regFile [sel_i1] = Ip1;
end
default: begin //If undefined
end
endcase
end
else;
end
else;
end
endmodule

B)
Verilog: The Module
Verilog designs consist of interconnected modules.
A module can be an element or collection of lower level design blocks.
A simple module with combinational logic might look like this:
module mux_2_to_1(a, b, out,
outbar, sel);
// This is 2:1 multiplexor
input a, b, sel;
output out, outbar;
assign out = sel ? a : b;
assign outbar = ~out;
endmodule
Example:
Lets take two 3 bit numbers A=010 and B=011 and input them in the full adder with both values
of control lines.

For K=0:
B0(exor)K=B0 and C0=K=0

Thus from first full adder

= A0+B0
= 0+1
= 1,

S0=1
C1=0
Similarly,
S1=0 with C2=1
S2=1 and C2=0

Thus,
A = 010 =2
B = 011 = 3
Sum = 0101 = 5
For K=1
B0(exor)K=B0' and C0=k=1

Thus
S0=1 and C1=0
Similarly
S1=1 and C2=0
S3=1 and c3=1

Thus,
A = 010 = 2
B = 011 = 3
Sum(Difference) = 1111 = -1
ANSWER OF QUESTION 5:
\\module name
module fsm(clock,reset,coin,vend,state,change);
\\these are the inputs and the outputs.
input clock;
input reset;
input [2:0]coin;
output vend;
output [2:0]state;
output [2:0]change;
6
\\i need to define the registers as change,coin and vend
reg vend;
reg [2:0]change;
wire [2:0]coin;
\\my coins are declared as parameters to make reading better.
parameter [2:0]NICKEL=3’b001;
parameter [2:0]DIME=3’b010;
parameter [2:0]NICKEL_DIME=3’b011;
parameter [2:0]DIME_DIME=3’b100;
parameter [2:0]QUARTER=3’b101;
\\MY STATES ARE ALSO PARAMETERS . I DONT WANT TO MAKE YOU READ
\\IN MACHINE LANGUAGE
parameter [2:0]IDLE=3’b000;
parameter [2:0]FIVE=3’b001;
parameter [2:0]TEN=3’b010;
parameter [2:0]FIFTEEN=3’b011;
parameter [2:0]TWENTY=3’b100;
parameter [2:0]TWENTYFIVE=3’b101;
\\AS ALWAYS THE STATES ARE DEFINED AS REG
reg [2:0]state,next_state;
\\MY MACHINE WORKS ON STATE AND COIN
always @(state or coin)
begin
next_state=0; \\VERYFIRST NEXT STATE IS GIVEN ZERO
case(state)
IDLE: case(coin) \\THIS IS THE IDLE STATE
NICKEL: next_state=FIVE;
DIME: next_state=TEN;
QUARTER: next_state=TWENTYFIVE;
default: next_state=IDLE;
endcase
FIVE: case(coin) \\THIS IS THE SECOND STATE
7
NICKEL: next_state=TEN;
DIME: next_state=FIFTEEN;
QUARTER: next_state=TWENTYFIVE; //change=NICKEL
default: next_state=FIVE;
endcase
TEN: case(coin) \\THIS IS THE THIRD STATE
NICKEL: next_state=FIFTEEN;
DIME: next_state=TWENTY;
QUARTER: next_state=TWENTYFIVE; //change=DIME
default: next_state=TEN;
endcase
FIFTEEN: case(coin) \\THIS IS THE FOURTH STATE
NICKEL: next_state=TWENTY;
DIME: next_state=TWENTYFIVE;
QUARTER: next_state=TWENTYFIVE; //change==NICKEL_DIME
default: next_state=FIFTEEN;
endcase
TWENTY: case(coin) \\THIS IS THE FIFTH STATE
NICKEL: next_state=TWENTYFIVE;
DIME: next_state=TWENTYFIVE; //change=NICKEL
QUARTER: next_state=TWENTYFIVE; //change==DIME_DIME
default: next_state=TWENTY;
endcase
TWENTYFIVE: next_state=IDLE; \\THE NEXT STATE HERE IS THE RESET
default : next_state=IDLE;
endcase
end
always @(clock)
begin \\WHENEVER I GIVE A RESET I HAVE TO MAKE THE STATE TO IDLE AND
VEND TO 1
if(reset) begin
state <= IDLE;
vend <= 1’b0;
// change <= 3’b000;
end \\THE CHANGE ALSO HAS TO BECOME NONE
else state <= next_state;
8
case (state) \\HERE WE DECIDE THE NEXT STATE
\\ALL THE STATES ARE DEFINED HERE AND THE OUTPUT IS ALSO GIVEN
IDLE: begin vend <= 1’b0; change <=3’d0; end
FIVE: begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL; else change <=3’d0; end
TEN: begin vend <= 1’b0; if (coin==QUARTER) change <=DIME; else change <= 3’d0; end
FIFTEEN : begin vend <= 1’b0; if (coin==QUARTER) change <=NICKEL_DIME; else change
<= 3’d0; end
TWENTY : begin vend <= 1’b0; if (coin==DIME) change <=NICKEL; else if
(coin==QUARTER) change <=DIME_DIME; else change <= 3’d0; end
TWENTYFIVE : begin vend <= 1’b1; change <=3’d0; end
default: state <= IDLE;
endcase
end
Endmodule

STATE DIAGRAM: