Register Transfer Level (RTL)

• Outputs are a function of current state and inputs

Current
State
State
Memory
Input Next
Inputs State D Q
Forming D Q
Logic

Output Outputs
Forming
Logic

© 2018 BYU ECEn 220 3

 The always_ff Block
• Contains the input forming logic for the flip
flops you are inferring.
• Uses a sensitivity list to describe when the
flip flops load the new values
– always_ff @(posedge clock)
• Body of always block will not evaluate until a
positive edge of the clock (positive edge FFs)
– always_ff @(negedge clock)
• Negative edge triggered flip-flops

© 2018 BYU ECEn 220 4

 Assignment Statements

• Use non-blocking assignment statements (<=)

• Flip-Flops will be inferred for all signals that

are assigned within always_ff blocks

• Can use “if” and “case” statements

– Do not need to cover all cases (memory
element will hold previous value)

© 2018 BYU ECEn 220 5

 1-Bit Flip-Flop

module ff(
input wire logic clk, d,
D Q
output logic q
d q
);

clk always_ff @(posedge clk)

q <= d;

endmodule

© 2018 BYU ECEn 220 6

 Loadable 1-Bit Flip-Flop

module ff(
input wire logic clk, load, d,
output logic q
0 );
D Q q
d 1
always_ff @(posedge clk)
if (load)
load
clk q <= d;

endmodule

if load is ‘1’, load d to q

else nothing happens

© 2018 BYU ECEn 220 7

 Flip-Flops and Logic

always_ff @(posedge clk)

begin
a<=b;
a <= b&c;
end

C D
B
B
Q A

clk CLK

© 2018 BYU ECEn 220 8

 D Flip-Flop with Asynchronous Reset

always_ff @(posedge clk

or negedge rst)
rst
begin
if (!rst) A <= 0; clr
else A <= B; B D
end
Q A
To make the reset synchronous, just
remove negedge rst from the
sensitivity list. clk CLK

© 2018 BYU ECEn 220 9

D Flip-flop with Synchronous Reset and
Enable

always_ff @(posedge clk)

begin
if (rst) rst D
B
A <= 0;
else if (enable) enable EN Q A
A <= B;
clk CLK
end

© 2018 BYU ECEn 220 10

 A Parameterized Loadable Register

module LoadableReg #(WID=4)(

input wire logic clk, load,
input logic[WID-1:0] din,
output logic[WID-1:0] myreg
0 );
D Q myreg
din 1
always_ff @(posedge clk)
if (load)
load myreg <= din;
clk

endmodule

© 2018 BYU ECEn 220 11

 A Shift Register

logic[3:0] Q;
always_ff @(posedge clk)
begin Q[3] <= Q[2];
Q <= {Q[2:0],Q[3]} Q[2] <= Q[1];
Q[1] <= Q[0];
end Q[0] <= Q[3];

Without a reset or D Q D Q D Q D Q
load, this circuit can D Q D Q D Q D Q
never be initialized. CLK CLK CLK CLK
CLK CLK CLK CLK
clk
clk

© 2018 BYU ECEn 220 12

 A Parameterized Counter

module upCnt #(WID=4)(

input wire logic clk,
output logic[WID-1:0] cnt
+1 4
D Q 4
cnt );

always_ff @(posedge clk)

cnt <= cnt + 1;
clk
endmodule
Without a clear or
load, this circuit can
never be initialized.
Must have a clr signal to reset it to 0.
Otherwise, cnt would be in X state on startup.

© 2018 BYU ECEn 220 13

 A Counter with a Clear

module upCnt #(WID=4)(

input wire logic clk, clr,
0 output logic[WID-1:0] cnt
+1
4
D Q 4
cnt );
0000 1

always_ff @(posedge clk)

clr if (clr)
clk cnt <= 0;
else
cnt <= cnt + 1;
endmodule

Must have a clr signal to reset it to 0.

Otherwise, cnt would be in X state on startup.

© 2018 BYU ECEn 220 14

 Current/Next State Values

module upCnt #(WID=4)(

input wire logic clk, clr,
0 output logic[WID-1:0] cnt
+1
4
D Q 4
cnt );
0000 1

always_ff @(posedge clk)

clr if (clr)
clk cnt <= 0;
else
cnt <= cnt + 1;
endmodule

© 2018 BYU ECEn 220 15

A Counter with Synchronous Reset and
Enable

parameter WID=8;
rst
logic[WID-1:0] count; clr
logic enable, reset; enable EN

always_ff @(posedge clk)

begin
if (reset)
count<=0;
count
else if (enable)
count<=count+1;
end

© 2018 BYU ECEn 220 16

 Another Counter
module upCnt #(WID=4)(
cnt 00 input wire logic clk, clr, inc,
4
cnt+1 01
4 D Q cnt output logic[WID-1:0] cnt
0 10 4 4
4
11
);
cnt 4
2
always_ff @(posedge clk)
clr inc clk
if ( )
cnt <= 0;
else if ( )
A. !clr && !inc cnt <= cnt + 1;
B. !clr && inc endmodule
C. clr && !inc
D. clr && inc

© 2018 BYU ECEn 220 17

 Another Counter
module upCnt #(WID=4)(
cnt 4 input wire logic clk, clr, inc,
cnt+1 output logic[WID-1:0] cnt
4 D Q cnt
0 4
4 4
);
cnt 4
2
always_ff @(posedge clk)
clr inc clk
if (clr && !inc)
cnt <= 0;
else if (!clr && inc)
cnt <= cnt + 1;
endmodule

© 2018 BYU ECEn 220 18

 Yet Another Counter
module upCnt #(WID=4)(
input wire logic clk,
input wire logic clr, inc,
0
0 output logic[WID-1:0] q
+1
1 4
D Q 4
q );
1
0000
inc always_ff @(posedge clk)
clk if (?)
clr
q <= 0;
else if (?)
q <= q + 1;
A. !clr
endmodule
B. clr
C. !inc
D. inc

© 2018 BYU ECEn 220 19

 Yet Another Counter

module upCnt #(WID=4)(

input wire logic clk,
input wire logic clr, inc,
0 output logic[WID-1:0] q
0
+1 );
1 4
D Q 4
q
1
0000 always_ff @(posedge clk)
inc if (clr)
clr clk q <= 0;
else if (inc)
q <= q + 1;
endmodule

© 2018 BYU ECEn 220 20

 A Swapper

module swapper (
input wire logic clk, load, swap,
0
0 input wire logic a, b,
1
D Q output logic out1, out2
a out1 );
1

swap
always_ff @(posedge clk)
load clk if (?)
begin
out1 <= a; A. !load
out2 <= b;
0
end B. load
0
D Q
else if (?)
begin C. !swap
1
b 1
out2 out1 <= out2;
out2 <= out1;
D. swap
end
swap
load clk endmodule

© 2018 BYU ECEn 220 21

 A Swapper

module swapper (
input wire logic clk, load, swap,
0
0 input wire logic a, b,
1
D Q output logic out1, out2
a out1 );
1

swap
always_ff @(posedge clk)
load clk if (load)
begin
out1 <= a;
out2 <= b;
end
0
0 else if (swap)
1
D Q begin
b out2 out1 <= out2;
1
out2 <= out1;
end
swap
load clk endmodule

© 2018 BYU ECEn 220 22

 Multiple Assignments to a Signal

• When you assign

twice…
– Last one takes module multiAssign (
input wire logic clk, clr,
effect on the signal output logic[3:0] cnt
);
value
always_ff @(posedge clk)
begin
cnt <= 4'b0000;
0 if (!clr)
+1 cnt <= cnt+1;
4
D Q 4
cnt
end
0000 1
endmodule

clr
clk

© 2018 BYU ECEn 220 23

 A Shift Register
module delay4 (
input wire logic clk, SerIn,
output logic[3:0] Q
Q[3] Q[2] Q[1] Q[0]
);

SerIn D Q D Q D Q D Q always_ff @(posedge clk)

Q <= ;
endmodule
CLK CLK CLK CLK
A.{SerIn, Q[2:0]}
B.{Q[3:1], SerIn}
C.{SerIn, Q[3:1]}
D.{Q[2:0], SerIn}
E.{Q[2:1], SerIn}

© 2018 BYU ECEn 220 24

 A Shift Register

module delay4 (
input wire logic clk, SerIn,
output logic[3:0] Q
Q[3] Q[2] Q[1] Q[0] );

SerIn D Q D Q D Q D Q always_ff @(posedge clk)

Q <= {SerIn, Q[3:1]};
endmodule
CLK CLK CLK CLK

© 2018 BYU ECEn 220 25

 Another Shift Register

module delay3 (
input wire logic clk,
input wire logic SerIn,
output logic Q
);
a b logic a, b;
SerIn D Q D Q D Q Q
always_ff @(posedge clk)
begin
CLK CLK CLK a <= SerIn;
b <= a;
Q <= b;
end
endmodule

© 2018 BYU ECEn 220 26

 Yet Another Shift Register

module delay3 (
input wire logic clk,
input wire logic SerIn,
output logic Q
);
logic a, b;
a b
SerIn D Q D Q D Q Q
always_ff @(posedge clk)
begin
Q <= b;
CLK CLK CLK
b <= a;
a <= SerIn;
end
endmodule
Order of assignments DOES NOT MATTER…

© 2018 BYU ECEn 220 27

 A Register File
module regFile (
Reg0 input wire logic clk, regWE,
n
input wire logic [2:0] Addr,
Reg1 n input wire logic [15:0] DataIn,
Register write signals

Reg2 output logic[15:0] DataOut

n

8:1 MUX
Write Reg3 );
n
Decoder DataOut
Reg4 n n=16
logic [15:0] registers [8];
Reg5
n
Reg6
n
// The synchronous write logic
Reg7
always_ff @(posedge clk)
n if (regWE)
m=3 n=16 registers[Addr] <= ;
regWE DataIn clk
// The asynchronous read logic
Addr
assign DataOut = ;

endmodule

© 2018 BYU ECEn 220 28

 A Register File

module regFile (
input wire logic clk, regWE,
Reg0 input wire logic [2:0] Addr,
n
Reg1
n input wire logic [15:0] DataIn,
Register write signals

Reg2 output logic[15:0] DataOut

n
Reg3
8:1 MUX );
Write n
Decoder DataOut
Reg4 n=16
n logic [15:0] registers [8];
Reg5
n
Reg6
n
// The synchronous write logic
Reg7 always_ff @(posedge clk)
n
if (regWE)
m=3 n=16 registers[Addr] <= DataIn;
regWE DataIn clk

Addr // The asynchronous read logic

assign DataOut = registers[Addr];

endmodule

© 2018 BYU ECEn 220 29

 module regFile (
input wire logic clk, regWE,

A Register File
input wire logic [2:0] Addr,
input wire logic [15:0] DataIn,
output logic[15:0] DataOut
);
logic[15:0] Reg0,Reg1,Reg2,Reg3,
Reg4,Reg5,Reg6,Reg7;

Reg0 // The synchronous write logic

n
Reg1 always_ff @(posedge clk)
n
Register write signals

if (regWE)
Reg2 case(Addr)
n

8:1 MUX
Reg3 3’b000: Reg0 <= DataIn;
Write n
Decoder DataOut 3’b001: Reg1 <= DataIn;
Reg4 n n=16 3’b010: Reg2 <= DataIn;
Reg5 3’b011: Reg3 <= DataIn;
n
3’b100: Reg4 <= DataIn;
Reg6
n 3’b101: Reg5 <= DataIn;
Reg7 3’b110: Reg6 <= DataIn;
n
default: Reg7 <= DataIn;
m=3 n=16 endcase
regWE DataIn clk
// The asynchronous read logic
Addr assign DataOut = (Addr==3’000)? Reg0:
(Addr==3’001)? Reg1:
…….
reg7;
endmodule
© 2018 BYU ECEn 220 30