Chapter 23

SystemVerilog State Machines

ECEn 220
Fundamentals of Digital Systems

© 2018 BYU
 Components of an FSM

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

Output Outputs
Forming
Logic

© 2018 BYU ECEn 220 2

 Components of a FSM

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

1. State memory
Output Outputs
• Flip-flops to hold the current state
Forming
• Sequential Logic
Logic

© 2018 BYU ECEn 220 3

 Components of a FSM

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

1. State memory
Output Outputs
• Flip-flops to hold the current state
Forming
• Sequential Logic
Logic
2. Input Forming Logic (IFL)
• Logic to determine the next state of the FSM
• Combinational Logic

© 2018 BYU ECEn 220 4

 Components of a FSM

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

1. State memory
Output Outputs
• Flip-flops to hold the current state
Forming
• Sequential Logic
Logic
2. Input Forming Logic (IFL)
• Logic to determine the next state of the FSM
• Combinational Logic
3. Output Forming Logic (OFL)
• Logic to determine FSM outputs
• Combinational logic
© 2018 BYU ECEn 220 5
 SystemVerilog FSMs

• SystemVerilog code is needed for each of the

three components of an FSM
– State FF code
– IFL code
– OFL code

© 2018 BYU ECEn 220 6

 State Machine Coding Styles
• One always_comb block for IFL and OFL and
one always_ff block for state register

• One always ff block for the state register

and IFL and the OFL is done using either
dataflow assign statements or an
always_comb block.

• Three separate blocks for the state register,

IFL, and ODL
© 2018 BYU ECEn 220 7
 Moore Output

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

Output Outputs
Forming
Logic

© 2018 BYU ECEn 220 8

 Enumerate the states typedef enum {s0, s1, s2, s3} StateType;
StateType ns, cs;

A Sequence Detector always_comb

begin
Xin ns = cs; // default
Z = 0; // default

if (reset)
reset ns = s0;
S0
else
Xin case (cs)
s0: if (!Xin)
ns = s1;
s1: if (Xin)
S3 Z S1 Xin ns = s2;
s2: if (Xin)
Xin ns = s3;
Xin else
ns = s1;
S2 Xin s3: Z = 1’b1; // Moore
endcase
end

always_ff @(posedge clk)

© 2018 BYU cs <= ns; 9
ECEn 220
 Moore Output
always_ff @(posedge clk)
cs <= ns;

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

Output Outputs
always_comb Forming
begin Logic

end

© 2018 BYU ECEn 220 10

 always_comb
begin

A Sequence Detector
ns = cs;
Z = 0;

Xin if (reset)
ns = s0;
else
case (cs)
reset s0: if (!Xin)
S0
ns = s1;
Xin s1: if (Xin)
ns = s2;
s2: if (Xin)
ns = s3;
S3 Z S1 Xin else
ns = s1;
Xin s3: Z = 1’b1;
Xin endcase
end
S2 Xin
Assign Z=(cs == S3) ? 1’b1 : 1’b0;
Use dataflow for Moore output
always_ff @(posedge clk)
cs <= ns;
© 2018 BYU 11
 typedef enum {S0, S1, S2, S3} StateType;

A Better Sequence
StateType ns, cs;
always_comb
Detector begin
ns = cs;
Z = 0;

if (reset)
reset Xin ns = S0;
else
Xin case (cs)
S0 S0: if (!Xin) ns = S1;
Xin Xin S1: if (Xin) ns = S2;
S2: if (Xin) ns = S3;
else ns = S1;
Xin S3: begin
Z S3 S1 Xin Z = 1’b1;
if (!Xin) ns = S1;
else ns = S0;
Xin Xin
end
endcase
S2 Xin
end
always_ff @(posedge clk)
cs <= ns;
© 2018 BYU 12
 State Transition and Output

© 2018 BYU ECEn 220 13

 typedef enum {sIdle, sToken, sSpray} StateType;
A Car Wash FSM StateType ns, cs;
always_comb
begin
TOKEN
ns = cs;
clrt = 0;
spray = 0;
reset
S_IDLE
if (reset)
TOKEN ns = sIdle;
else
case (cs)
sIdle: if (token) ns = sToken;
S_TOKEN CLRT
TDONE sToken: begin
clrt = 1;
ns = sSpray;
end
SPRAY S_SPRAY
sSpray: begin
spray = 1;
if (tdone) ns = sIdle;
end
TDONE default: ns = sIdle;
endcase
end
always_ff @(posedge clk)
© 2018 BYU 14
cs <= ns;
 State Transition and Output

© 2018 BYU ECEn 220 15

 Mealy Output

Current
State State
Next Memory
Input State
Inputs D Q
Forming D Q
Logic

Output Outputs
Forming
Logic

© 2018 BYU ECEn 220 16

 Sequence typedef enum {s0, s1, s2} stateType
Detector with stateType ns, cs;
Mealy Output always_comb
begin
Xin ns = cs;
Z = 0;
if (reset)
ns = s0;
reset else
S0 case (state)
Xin s0: if (!Xin) ns = s1;
s1: if (Xin) ns = s2;
s2: if (Xin)
begin
Xin / Z S1 Xin ns = s0;
Z = 1; // Mealy output
end
Xin else ns = s1;
endcase
S2 Xin
end

always_ff @(posedge clk)

cs <= ns;

© 2018 BYU ECEn 220 17

 typedef enum {s0, s1, s2, ERR=’X} stateType

Defensive Coding
stateType ns, cs;

Style always_comb
begin
Xin ns = ERR;
Z = 0;
if (reset)
ns = s0;
reset else
S0 case (state)
Xin s0: if (!Xin) ns = s1;
else ns = s0;
s1: if (Xin) ns = s2;
else ns = s1;
Xin / Z S1 Xin s2: if (Xin)
begin
ns = s0;
Xin Z = 1; // Mealy output
end
S2 Xin
else ns = s1;
endcase
end

always_ff @(posedge clk)

© 2018 BYU cs <= ns; 18
 State Transition and Output

© 2018 BYU ECEn 220 19

 Xin

Input Forming Logic Xin

S0
Xin
Xin

• Both Combinational and Z S3

Xin
S1 Xin
Sequential Logic
Xin Xin

S2 Xin
always_ff @(posedge clk)
case (current_state)
S0: if (Xin == 1’b0) current_state <= S1
S1: if (Xin == 1’b1) current_state <= S2
S2: if (Xin == 1’b1) current_state <= S3
else current_state <= S1;
S3: if (Xin == 1’b0) current_state <= S1
else current_state <= S0;
endcase

© 2018 BYU ECEn 220 20

 always_ff @(posedge clk)
case (current_state)
module sequence(
S0: if (Xin == 1’b0) current_state <= S1;
input logic clk,Xin,
S1: if (Xin == 1’b1) current_state <= S2;
output logic Z
S2: if (Xin == 1’b1) current_state <= S3;
); else current_state <= S1;
S3: if (Xin == 1’b0) current_state <= S1;
typedef enum {S0, S1, S2, S3} StateType;
else current_state <= S0;
StateType next_state, current_state = S0;
endcase

assign Z = (current_state == S3);

endmodule

CLK

Xin

current
S0 S0 S1 S1 S2 S3 S1 S2
_state

© 2018 BYU ECEn 220 21

 Can IFL, State FFs, and OFL be
combined?
always_ff @(posedge clk) Problem:
begin A FF will be generated for the ‘Z’ output
Z <= 1’b0;
(all signals assigned in a clocked
case (current_state)
S0:
always process will have an FF).
if (Xin == 1’b0) current_state <= S1;
S1:
if (Xin == 1’b1) current_state <= S2;
S2:
if (Xin == 1’b1) current_state <= S3;
else current_state <= S1;
S3: begin
Z <= 1’b1;
if (Xin == 1’b0) current_state <= S1;
else current_state <= S0; An FF on the output Z will cause the
end
signal to be delayed by one clock
endcase
end cycle. The output will no longer be
asserted during the S3 state, but
during the following cycle.
© 2018 BYU ECEn 220 22
module sequence( S0: if (Xin == 1’b0) current_state <= S1;
input logic clk, Xin, else current_state <= S0;
output logic Z S1: if (Xin == 1’b1) current_state <= S2;
); else current_state <= S1;
S2: if (Xin == 1’b1) current_state <= S3;
typedef enum {S0, S1, S2, S3} StateType; else current_state <= S1;
StateType next_state, current_state = S0; S3: begin
Z <= 1’b1;
always_ff@(posedge clk) begin if (Xin == 1’b0) current_state <= S1;
Z <= 1’b0; else current_state <= S0;
case (current_state) end
endcase
end
endmodule

CLK

Xin

current
S0 S0 S1 S1 S2 S3 S1 S2
_state

© 2018 BYU ECEn 220 23