FINITE STATE MACHINES

Door Ex: State Diagram

Transition
Condition
(a)Conventional Synchronous FSM (b)Conventional Asynchronous FSM

• Typically used in digital circuit design for modelling sequential designs.

A hardware implementation requires a register to store state variables, a
block of combinational logic that determines the state transition, and a
second block of combinational logic that determines the output of an FSM.
Moore Circuit Example
Y = QB’ +QA

Thus, Y does not depend on input A

Mealy Circuit Example
Y = QB’ + QA + A

Thus, Y depends on input A as well as states.

In general, a FSM VHDL code has two process
statements. One each for:

• Clocking Scheme and Reset Mechanism

• Next State Evaluation

 Clocking Scheme and Reset Mechanism

Assume that Initially state0 =1 and nx_state =0

reset

pr_state
FSM for Clk Gen
clock (State evaluation)

reset

clock

pr_state nx_state
state0
Next State
Evaluation
I0/O0

S0

I0/O0
I1/O1

S1

I1/O1

I2/O2
S2

I2/O2
BCD Counter Example

STATE

OUTPUT
Example 2
Example 3 : LED controlled by Toggle Switch
Example 4 : LED controlled by On-Off Switch
Example 5
 Example 6

Identify the circuit from State Transition Diagram and write description