DDW-103 Diseño Digital

Prof. David Márquez Viloria

Sequencing and Control

Mano and Kime

Sections 8-1 – 8-7
 Sequencing and Control

Algorithmic State Machines

Binary Multiplier
Hardwired Control
Binary Multiplier – VHDL
Microprogrammed Control
Algorithmic State Machine
ASM Block

Timing
 Sequencing and Control

Algorithmic State Machines

Binary Multiplier
Hardwired Control
Binary Multiplier – VHDL
Microprogrammed Control
An Algorithmic Binary Multiplier

Either adding the

multiplier or 0000
Shifting partial product right
is the same as shifting the
multiplier to the left
If GO Then

Initialize the multiplier

Begin in state MUL0
If the right-most bit of the multiplier
in the Q shift register is 0 then
goto state MUL1
Otherwise, if the right-most bit
of the multiplier is 1 then
add the partial product (A)
to the multiplicand (B) and store
it in A. Prepare to shift in C.
Shift a 0 into C, shift right
C || A || Q into C || A || Q
Decrement P

C || A || Q denotes a composite
register.
If Z = 1 then we have gone
through the state machine
n -1 times and we are finished
Otherwise, if Z = 0 we continue
back to state MUL0.
Register A contains the four
most significant bits of the
product and Register Q contains
the four least significant bits of
the product when we are finished.

Note that n-bits x n-bits <= 2n bits

 Sequencing and Control

Algorithmic State Machines

Binary Multiplier
Hardwired Control
Binary Multiplier – VHDL
Microprogrammed Control
Let’s take a closer look at the
control unit
Sequencing State Machine
Decoder outputs based off of
the present state

--The decoder plays role in

controlling the next state
00
01
10
ASM chart transformation
rules with one flip-flop
per state

Notice two flip flops for

the two states, MUL0 and
MUL1
Idle Junction
(from Z and G)

Idle State

Decision Box

junction

State MUL0

State MUL1

Z Decision Box
 Sequencing and Control

Algorithmic State Machines

Binary Multiplier
Hardwired Control
Binary Multiplier – VHDL
Microprogrammed Control
VHDL

-- Binary Multiplier with n=4; VHDL Description

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity binary_multiplier is
port(CLK, RESET, G, LOADB, LOADQ: in std_logic;
MULT_IN: in std_logic_vector(3 downto 0);
MULT_OUT: out std_logic_vector(7 downto 0));
end binary_multiplier;
architecture behavior_4 of binary_multiplier is
type state_type is (IDLE, MUL0, MUL1);
signal state, next_state : state_type;
signal A, B, Q: std_logic_vector(3 downto 0);
signal P : std_logic_vector(1 downto 0);
signal C, Z: std_logic;

begin
Z <= P(1) NOR P(0);
MULT_OUT <= A & Q;
State Machine
state_register: process (CLK, RESET)
begin
if (RESET = ‘1’) then
state <= IDLE;
elsif (CLK’event and CLK = ‘1’) then
state <= next_state;
end if;
end process;
next_state_func: process (G, Z, state)
begin
case state is
when IDLE =>
if G = ‘1’ then
next_state <= MUL0;
else
next_state <= IDLE;
end if; Next State
when MUL0 =>
next_state <= MUL1;
when MUL1 =>
if Z = ‘1’ then
next_state <= IDLE;
else
next_state <= MUL0;
end if;
end case;
end process;
DATAPATH
datapath_func: process (CLK)
variable CA: std_logic_vector(4 downto 0);
begin
if (CLK’event and CLK = ‘1’) then
if LOADB = ‘1’ then
B <= MULT_IN;
end if; when MUL1 =>
if LOADQ = ‘1’ then C <= ‘0’;
Q <= MULT_IN; A <= C & A(3 downto 1);
end if; Q <= A(0) & Q(3 downto 1);
case state is P <= P - “01”;
when IDLE => end case;
if G = ‘1’ then end if;
C <= ‘0’; end process;
A <= “0000”; end behavior_4;
P <= “11”;
end if;
when MUL0 =>
if Q(0) = ‘1’ then
CA := (‘0’ & A) + (‘0’ & B);
else
CA := C & A;
end if;
C <= CA(4);
A <= CA(3 downto 0);
 Problem 2
Assuming ASM chart given on the next slide,
supplement timing waveforms given in the
answer sheet with the correct values of
signals
State, g1, g2, g3, in the interval from 0 to 575
ns.
 ASM Chart
Reset

Idle

1
r1

0 gnt1 1
0
g1 r1

1
r2
0 gnt2 1
0
g2 r2

0 1
r3
gnt3 1
0
g3 r3
Reset

Clk

r1

r2

r3

State
g1

g2

g3
0 ns 100 ns 200 ns 300 ns 400 ns 500 ns
 ASM Summary by Prof. Chu
• ASM (algorithmic state machine) chart
– Flowchart-like diagram
– Provides the same info as a state diagram
– More descriptive, better for complex description
– ASM block
• One state box
• One or more optional decision boxes:
with T (1) or F (0) exit path
• One or more conditional output boxes:
for Mealy output
38
 ASM Chart Rules
• Difference between a regular flowchart
and an ASM chart:
– Transition governed by clock
– Transition occurs between ASM blocks
• Basic rules:
– For a given input combination, there is one
unique exit path from the current ASM block
– Any closed loop in an ASM chart must
include a state box

Based on RTL Hardware Design by P. Chu

Incorrect ASM Charts

Based on RTL Hardware Design by P. Chu

Generalized FSM

Based on RTL Hardware Design by P. Chu

Alternative Coding Styles
by Dr. Chu
(to be used with caution)
 Traditional Coding Style
process(clock, reset)
Inputs Next State
function
Next State

clock Present State Present State

reset Register

Mealy Output Moore Output concurrent

function function statements

Mealy Outputs Moore Outputs

 Alternative Coding Style 1
Process(Present State, Inputs)
Inputs Next State
function
Next State
Process(clock, reset)
clock Present State Present State
reset Register
Process(Present
State, Inputs) Process(Present State)
Mealy Output Moore Output
function function

Mealy Outputs Moore Outputs

oe<=1

oe<=1

oe<=1

oe<=1

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48
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50
 Alternative Coding Style 2
Process(Present State,Inputs)

Process(clk, reset)
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