Introduction to Digital System Design

Prof. David Márquez Viloria

 Outline

• Introduction to digital signals and systems

• Introduction to hardware architectures

• Register Transfer Level (RTL)

• High Level Synthesis (HLS)

• Examples
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
Digital signals and systems
 Digital signals and systems

Analog to Digital Conversion (ADC)

 Introduction to Hardware Architecture
History of computing hardware:
Abacus (2700 BC)
Jhon Napier, slide rule 1620 Blaise Pascal, mechanical calculator 1642

Charles Babbage, First general-

purpose computing device,
difference engine 1833 George Boole (Boolean algebra)
The Mathematical Analysis of Logic (1847),
An Investigation of the Laws of Thought
(1854)
 Introduction to Hardware Architecture
History of computing hardware:
Vacuum tube, 1904 British cryptologists decipher German Enigma-
machine-encrypted 1939,
Alan Turing, Turing machine 1936

Electromechanical Konrad Zuse, Zuze Z3 1940

 Introduction to Hardware Architecture
History of computing hardware:

Colossus 1944 ENIAC 1945

 Introduction to Hardware Architecture
History of computing hardware:

John Bardeen, William
Shockley and Walter
Brattain at Bell Labs. They
invented the point-contact
transistor in 1947
Bipolar junction transistor in 1948
The die from an Intel 8742, an 8-bit
microcontroller that includes a CPU
running at 12 MHz, 128 bytes of RAM,
2048 bytes of EPROM, and I/O in the
same chip, 1976
 Introduction to Hardware Architecture
History of computing hardware:

Fairchild Semiconductor
International, Inc. 1957
 Introduction to Hardware Architecture
The Von Neumann Architecture: Arduino architecture
 Introduction to Hardware Architecture
Multi-core processors
 Introduction to Hardware Architecture
Graphics processing unit (GPU)
 Introduction to Hardware Architecture
Field Programmable Gate Arrays (FPGAs) Arquitecture
 Digital Design on FPGA
Register-transfer Level (RTL):
RTL is a design abstraction which models a synchronous digital circuit in terms of the flow of
digital signals (data) between hardware registers, and the logical operations performed on
those signals.

Xilinx Vivado Design Suite

 Digital Design on FPGA
Register-transfer Level (RTL):
 Digital Design on FPGA
Hardware Description Languages (HDLs): Register-transfer-level abstraction is used in
hardware description languages (HDLs) like Verilog and VHDL to create high-level
representations of a circuit.
VHDL (VHSIC-HDL, Very High Speed Integrated Circuit Hardware Description Language)
 Digital Design on FPGA
Control Unit: Finite state machine (FSM) and Algorithmic state machine (ASM)
Digital Design on FPGA
 Digital Design on FPGA
Control Unit: Finite state machine (FSM) and Algorithmic state machine (ASM)
 High-Level Synthesis: HLS

High-Level Synthesis
• Creates an RTL implementation from C, C++,
System C, OpenCL API C kernel code
• Extracts control and dataflow from the source
code
• Implements the design based on defaults and
user applied directives

Many implementation are possible

from the same source description
• Smaller designs, faster designs, optimal designs
• Enables design exploration

Intro to HLS 11- 36 © Copyright 2016 Xilinx

 Design Exploration with Directives
…
loop: for (i=3;i>=0;i--) {
if (i==0) {
One body of code: acc+=x*c[0]; Before we get into details, let’s look under
shift_reg[0]=x;
Many hardware outcomes } else { the hood ….
shift_reg[i]=shift_reg[i-1];
acc+=shift_reg[i]*c[i];
}
}
….

The same hardware is used for each iteration of the loop: Different hardware is used for each iteration of the loop: Different iterations are executed concurrently:
•Small area •Higher area •Higher area
•Long latency •Short latency •Short latency
•Low throughput •Better throughput •Best throughput

Intro to HLS 11- 37 © Copyright 2016 Xilinx

High-Level Synthesis : Pipelining the top-level function
Base desig
n
throughput
1.2Gb/s

Pipelined
throughpu
t
4.7Gb/s

Unrolled
throughpu
t
120Gb/s

Fu l l y
pipelined
throughpu
 Examples
Analysis on Numerical Representation of DSP for Optical Communications Aiming Minimum Hardware
Resources Utilization in SoC-FPGA.
CuPUs for CMA and MMA blind equalizers
 Examples
Analysis on Numerical Representation of DSP for Optical Communications Aiming Minimum Hardware
Resources Utilization in SoC-FPGA.
 Examples
Analysis on Numerical Representation of DSP for Optical Communications Aiming Minimum Hardware
Resources Utilization in SoC-FPGA.
 Examples
Analysis on Numerical Representation of DSP for Optical Communications Aiming Minimum Hardware
Resources Utilization in SoC-FPGA.
 Examples
Scalable Multi-Core FPGA Design for Maximum Concurrency: The Case of KNN for ICI Mitigation
 Examples
Scalable Multi-Core FPGA Design for Maximum Concurrency: The Case of KNN for ICI Mitigation
 Otros ejemplos

Mejoramiento de la percepción visual en robots humanoides usando arquitecturas heterogéneas para

aplicaciones autónomas
 Otros ejemplos

Mejoramiento de la percepción visual en robots humanoides usando arquitecturas heterogéneas para

aplicaciones autónomas
 Otros ejemplos

Mejoramiento de la percepción visual en robots humanoides usando arquitecturas heterogéneas para

aplicaciones autónomas