Shift register

Code:
entity Shiftreg is

Port ( clk : in STD_LOGIC;

il : in STD_LOGIC;

ir : in STD_LOGIC;

rst : in STD_LOGIC;

mode : in STD_LOGIC_vector(1 downto 0);

i : in STD_LOGIC_vector(3 downto 0);

q : out STD_LOGIC_vector(3 downto 0));

end Shiftreg;

architecture Behavioral of Shiftreg is

begin

process(clk,rst)

variable qtmp:std_logic_vector(3 downto 0);

begin

if rst='1' then

qtmp:="0000";

elsif(clk='1' AND clk' event) then

case mode is

when "00" =>qtmp :=qtmp;

when "01" =>qtmp:=i;

when "10" =>qtmp:=qtmp(2 downto 0) & ir;--left shift

when "11" =>qtmp:=il & qtmp(3 downto 1);--right shift

when others => null;

end case;

end if;

q<=qtmp;

end process;

end Behavioral;
TB code:
--Inputs

signal clk : std_logic := '0';

signal il : std_logic := '0';

signal ir : std_logic := '0';

signal rst : std_logic := '0';

signal mode : std_logic_vector(1 downto 0) := (others => '0');

signal i : std_logic_vector(3 downto 0) := (others => '0');

--Outputs

signal q : std_logic_vector(3 downto 0);

-- Clock period definitions

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: Shiftreg PORT MAP (

clk => clk,

il => il,

ir => ir,

rst => rst,

mode => mode,

i => i,

q => q

);

-- Clock process definitions

process(clk,rst)

begin
rst<='0';

rst<='0' after 70ns;

clk<=not clk after 20ns;

end process;

process

begin

i<="1010";wait for 100ns;

mode<="00";wait for 100ns;

mode<="01";wait for 100ns;

mode<="10";wait for 100ns;

ir<='1';wait for 100ns;

mode<="11";wait for 100ns;

il<='1';wait for 100ns;

end process;

END;

Output: