entity mod_n1v is

Generic(N:Integer:=4);
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (N-1 downto 0));
end mod_n1v;

architecture Behavioral of mod_n1v is

signal count1: std_logic_vector(N-1 downto 0);

signal clkout: std_logic;

signal count: Integer range 0 to 49999999:=0;

begin
--process( clk,reset)
--begin
--if reset='1' then
--clkout<='0';
--count <=0;
--elsif(clk' event and clk='1') then
--if(count = 49999999) then
--clkout <= not clkout;
--count <= 0;
--else
--count <= count+1;
--end if;
--end if;
--end process;

process(clk , reset)
begin
if (reset='1') then
count1<=(others=>'0');
elsif(clk'event and clk='1')then
if(enable='1')then
count1 <= count1+'1';
end if;
end if;
q <= count1;
end process;
end Behavioral;

Test Bench

entity test_mod is
-- Port ( );
end test_mod;

architecture Behavioral of test_mod is

component mod_n1v port(
clk : in STD_LOGIC;
reset : in STD_LOGIC;
enable : in STD_LOGIC;
q : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal clk :std_logic:='0';
signal reset :std_logic:='0';
 signal enable :std_logic:='0';
signal q :std_logic_vector(3 downto 0);
constant clock_period : time:= 20 ns;
begin
uut: mod_n1v port map(
clk => clk,
reset => reset,
enable=> enable,
q=> q);
process
begin
clk <= '1';
wait for clock_period/2;
clk<='0';
wait for clock_period/2;
end process;
process
begin
reset<='1';
wait for 10ns;

reset<= not reset;

enable<='1';
wait for 100ns;
wait;
end process;
end Behavioral;