Chapter 7 Latches and Flip-Flops

Chen, Yuanyuan
chenyuanyuan@scu.edu.cn

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• Examples

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 Problem
• Implement a loop counter that counts 0 to 9 and
then goes around. The results are shown by one 7-
segment display.

It is a sequential logic circuit.

Question: How to determine the time interval?

That is to say, when does the display switch to
the next number?
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 Combinational vs. Sequential Circuits

n-inputs Combinational m-outputs

Circuit (Depend only on inputs)
Combinational Circuit

n-inputs m-outputs
Combinational
Circuit Storage
Elements Present
Next state
state

Sequential Circuit

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 Sequential logic circuit

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 Flip-flops
• Flip-flops (latch)
 Have two stable states.
 It can be used to store state information.
 The basic storage element in sequential logic.
• Type of FF
 SR
 D
 JK
 T
• Type of triggering
 Untriggered (asynchronous)
 Level-triggered (C=1)
 Edge-triggered (rising or falling edge of Clock)

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A latch is a temporary storage device that has two
stable states (bistable). It is a basic form of memory.

The S-R (Set-Reset) latch is the most basic type. It can be

constructed from NOR gates or NAND gates. With NOR
gates, the latch responds to active-HIGH inputs; with
NAND gates, it responds to active-LOW inputs.

R S
Q Q

Q Q
S R
NOR Active-HIGH Latch NAND Active-LOW Latch
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 • RS

Logic symbol
“NAND”version

Logic symbol

“NOR”version
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 Edge triggered D Flip-flop

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• Edge Triggered Flip-flops
• An edge-triggered flip-flop changes states either at the positive edge
(rising edge) or at the negative edge (falling edge) of the clock pulse on
the control input.
e.g.
7 Complete
CPthe positive edge triggered D flip-flop’timing diagram.
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CP
1 2 3 4
0
t
D

0
t
Q

0
t
 Edge triggered T Flip-flop

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 Edge-triggered T Flip flop

e.g. Complete the negative edge triggered T flip-flop’

timing diagram.
 Edge triggered JK Flip-flop

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 Edge-triggered JK Flip flop

Complete the positive edge triggered JK flip-flop’

timing diagram.

CP

J
K
Q
 Edge triggered SR Flip-flop

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Characteristic equations compare
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 exercise
1. Complete the positive edge triggered D flip-flop’ timing diagram.

CP

2. Complete the negative edge triggered T flip-flop’ timing diagram.

CP

Q
 exercise
1. Complete the positive edge triggered D flip-flop’ timing diagram.

CP

2. Complete the negative edge triggered T flip-flop’ timing diagram.

CP

Q
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