CHAPTER 3

FLIP FLOPs AND

APPLICATION
JAPAN MALAYSIA TECHNICAL INSTITUTE (JMTI)
TKE
FLIP FLOP & APPLICATIONS
INTRODUCTION

Engineers classify logic circuits into two groups. We have already

worked with combination logic circuits using AND, OR, and NOT gates.
The other group of circuits is classified as sequential logic circuit.
Sequential circuits involve timing and memory devices.
The basic building block for combinational logic circuits is the logic gate.
The basic building block for sequential logic circuits is the flip-flop (FF).
 FLIP FLOP & APPLICATIONS
 Sequential Logic Circuits
Sequential Logic Circuits use flip-flops as memory elements and in which their
output is dependent on the input state

Combinational
outputs Memory outputs

Combinational Memory
logic elements

External inputs

Sequential circuit = Combinational logic + Memory Elements

Combinational Logic

 Output depends only on current input

 Able to perform useful operations
(add/subtract/multiply/…)
 Has no memory
Sequential Logic

 Output depends not only on current input but also

on past input values, e.g. design a counter
 Need some type of memory to remember the past
input values
Sequential Logic Concept
 Sequential Logic Circuits remember past inputs and
past circuit state.

 Outputs from the system are “feed back” as new

inputs
 With gate delay and wire delay

 The storage elements are circuits that are capable of

storing binary information: memory
Synchronous vs Asynchronous
There are two types of sequential circuits:

 Synchronous sequential circuit: circuit output changes

only at some discrete instants of time. This type of
circuits achieves synchronization by using a timing signal
called the clock.
[Outputs change only at specific time]

 Asynchronous sequential circuit: circuit output can

changes at any time (clockless)
[Outputs change at any time]
Clock Signal

 Clock generator: Periodic train of clock pulses

Different duty cycles

 Multivibrator: a class of sequential circuits. They can
be:
bistable (2 stable states)
monostable or one-shot (1 stable state)
astable (no stable state)

 Bistable logic devices: latches and

flip-flops.
 Latches and flip-flops differ in the method used for
changing their state.
Memory Elements
 Memory element: a device which can remember value
indefinitely, or change value on command from its inputs.

 Characteristic table:

Q(t): current state

Q(t+1) or Q+: next state

Memory Elements
Memory Elements
 Memory element with clock. Flip-flops are memory elements
that change state on clock signals.

Memory Q
command element stored value

clock

 Clock is usually a square wave.

Positive pulses

Positive edges Negative edges

Memory Elements
 Two types of triggering/activation:
 pulse-triggered
 edge-triggered
 Pulse-triggered
 latches
 ON = 1, OFF = 0
 Edge-triggered
 flip-flops
 positive edge-triggered (ON = from 0 to 1; OFF = other
time)
 negative edge-triggered (ON = from 1 to 0; OFF = other
time)
Latches
 A latches is a temporary storage device that has two stable state (bistable). It
is a basic form of memory.
 The S-R (Set-Reset) latch is the most basic type. It can be constructed from
NOR gates or NAND gates. With NOR gates the latch responds to active-HIGH
inputs; with NAND gates, it responds to active-LOW inputs.

 NOR gate Active-HIGH Latch (RS Latch)

Logic Circuit Logic Symbol Characteristic Table

 The active HIGH RS Latch is in a stable (latched) condition when both inputs
are LOW.
Latches
 NAND gate Active-LOW Latch (SR Latch)

NAND Active-LOW Latch

Characteristic Table
Logic Circuit

 The active Low SR Latch is in a stable (latched) condition when both inputs
are HIGH.
Gated SR Latch
 A gated latch is a variation on the basic latch.
 The gated latch has an additional input, called enable (En) that must be HIGH in order
for the latch to respond to the S and R inputs.
En = 1

Logic Symbol Characteristic Table

Logic Diagram

Timing Diagram
Gated D Latch
 The D latch is an variation of the SR latch but combines the S and R inputs
into a single D input as shown:

Characteristic Table

Logic Diagram Logic Symbol

Timing Diagram
Latch Circuits: Not Suitable
 Latch circuits are not suitable in synchronous logic
circuits.
 When the enable signal is active, the excitation inputs are
gated directly to the output Q. Thus, any change in the
excitation input immediately causes a change in the latch
output.
 The problem is solved by using a special timing control
signal called a clock to restrict the times at which the
states of the memory elements may change.
 This leads us to the edge-triggered memory elements
called flip-flops.
Flip Flops
 Flip-flops: synchronous bistable devices
 Output changes state at a specified point on a triggering input called the
clock.
 Change state either at the positive edge (rising edge) or at the negative edge
(falling edge) of the clock signal.

Clock signal

Positive edges Negative edges

Flip-flops
 A flip-flop differs from a latch in the manner it changes states. A flip-flop is a
clocked device, in which only the clock edge determines when a new bit is
entered.
 The active edge can be positive or negative.
Flip-flops
SR Flip-flop
 It comprises 3 parts:
 a basic NAND latch
 a pulse-steering circuit
 a pulse transition detector (or edge detector) circuit
 The pulse transition detector detects a rising (or falling)
edge and produces a very short-duration spike.
SR Flip-flop
 The pulse transition detector.

S
Q
Pulse
CLK transition
detector
Q'
R

CLK' CLK'
CLK CLK* CLK CLK*

CLK CLK

CLK' CLK'

CLK* CLK*

Positive-going transition Negative-going transition

(rising edge) (falling edge)
SR Flip-flop
D Flip-flop
D S Q
 D flip-flop: single input D (data) CLK
C
R
 D=HIGH a SET state Q'

 D=LOW a RESET state

A positive edge-triggered D flip-flop
 Q follows D at the clock edge. formed with an S-R flip-flop.

 Convert S-R flip-flop into a D flip-flop: add an inverter.

D CLK Q(t+1) Comments

1  1 Set
0  0 Reset
D Flip-flop
JK Flip-flop
 The J-K flip-flop is more versatile than the D flip-flop. In
addition to the clock input, it has two inputs, labelled J and K.
When both J and K = 1, the output changes states (toggles) on
the active clock edge (in this case, the rising edge).
 J-K flip-flop: Q and Q' are fed back to the pulse-steering NAND
gates.
 No invalid state.

Logic Circuit
T Flip-flop
 T flip-flop: single-input version of the J-K flip flop, formed by tying
both inputs together.

T
Q T J
Pulse Q
transition C
CLK CLK
detector K
Q' Q'

 Characteristic table.
T CLK Q(t+1) Comments Q T Q(t+1)
0  Q(t) No change 0 0 0
1  Q(t)' Toggle 0 1 1
1 0 1
1 1 0
 Application: Frequency division

T Flip-flop
Asynchronous Inputs
 S-R, D and J-K inputs are synchronous inputs, as data on
these inputs are transferred to the flip-flop’s output only
on the triggered edge of the clock pulse.
 Asynchronous inputs affect the state of the flip-flop
independent of the clock; example: preset (PRE) and
clear (CLR) [or direct set (SD) and direct reset (RD)]
 When PRE=HIGH, Q is immediately set to HIGH.
 When CLR=HIGH, Q is immediately cleared to LOW.
 Flip-flop in normal operation mode when both PRE and
CLR are LOW.
Asynchronous Inputs
 A J-K flip-flop with active-LOW preset and clear inputs.

PRE PRE

J
Q
J Q Pulse
C transition
CLK
K detector
Q' Q'
K

CLR CLR

CLK

PRE

CLR
Q
J=K=HIGH Preset Toggle Clear
Asynchronous Inputs
SR Flip Flop with Pre & Clr Input Active
Low

Logic Symbol

Characteristic Table
JK Master Slave
JK Master Slave

Characteristic Table JK Master Slave

END