FLIPFLOPS

• The memory elements are devices capable of storing binary info.

• The input and the present information stored in the memory element
determines the output of the sequential circuit.
• Flip flops are the memory elements in sequential logic circuits.
• Adder, subtractor, multiplexer, demultiplexer, decoder, ecoder etc are
examples for combinational logic circuits while counters, shift
registes, flip flops, sequence generators etc are the examples for
sequential logic circuits.
 Classification of sequential circuits
• Synchronous sequential circuits : Sequential circuits which are
controlled by a clock are called synchronous sequential circuits. These
circuits will be active only when clock signal is present.
outputs are produced at same instants of time.( period of clock
signal).
• Asynchronous sequential circuits : Sequential circuits which are not
controlled by a clock are called asynchronous sequential circuits.
outputs are generated at different instants of time.
 Flip flops
• A digital computer needs devices which can store information.
• A flip flop is a binary storage device. It can store binary bit either 0 or 1.
• It has two stable states, HIGH and LOW i.e. 1 and 0.
• It has the property to remain in one state indefinitely until it is directed
by an input signal to switch over to the other state.
• It’s function is same as that of bistable multivibrator.
• The basic formation of flip flop is to store data. They can be used to
keep a record of variable (input, output).
• Do you know!! computers and calculators use Flip flops for their
memory. A combination of number of flip flops will produce some
amount of memory.
• Flip flops is formed using logic gates, which are in turn made of
transistors.
• Flip flops are basic building blocks in the memory of electronic
devices. Each Flip flop can store one bit of data.
• There are different types of flip flops. They are SR flip flop, Clocked SR
flip flop, JK flip flop, JK master slave flip flop and T flip flop.
• Unclocked flip flops are sometimes called as LATCHES.
 RS Flip flop
• The RS (Reset Set) flip flop (also called as SR flip flop) is the simplest flip
flop of all and easiest to understand.
• It has two outputs. one output being the inverse or complement of the
other, and two inputs.
• A pulse on one of the inputs will result in a particular output.
• The outputs will then remain in this state until a pulse is applied to the
other input.
• The two inputs are called the Set and Reset input.
• Since RS flip flop is not clocked, they are also known as RS latch.
• (Latches are used in the asynchronous seq.cir while flipflops are used in
sync.seq.cir)
RS flipflop can be formed by using
1. NAND gates
2. NOR Gates
 Clocked RS Flip Flop
• The RS latch flip flop required the direct input but no clock. It is very
useful to add clock to control precisely the time at which the flip flop
changes the state of its output.
• In the clocked R-S flip flop the appropriate levels applied to their inputs
are blocked till the receipt of a pulse from an other source called clock.
• The flip flop changes state only when clock pulse is applied depending
upon the inputs
• This circuit is formed by adding two NAND gates at inputs to the R-S flip
flop.
• addition to control inputs Set (S) and Reset (R), there is a clock input (C)
also.
Truth Table
CLK R S Q Q-
0 0 0 No change No change
0 0 1 No change No change
0 1 0 No change No change
0 1 1 No change No change
1 0 0 No change No change
[Qn+1=Qn]
1 0 1 1 0
1 1 0 0 1
1 1 1 Indeterminate Indeterminate
D Flip Flop

• A D type (Data or delay flip flop) has a single data input in addition to the
clock input.
• Basically, such type of flip flop is a modification of clocked RS flip flop.
• The D input goes directly to S input and its complement through NOT
gate, is applied to the R input.
• There are two outputs and these outputs are complement to each other.
• D flip flop will work depending on the clock signal. ( Synchronous )
• When the clock is low there will be no change in the output of the flip
flop i.e. it remembers the previous state.
• When the clock is low, output Q is independent of input D.
• On the other hand, when the clock is high, Q is forced equal to D.
• when the clock again goes low, Q retains or stores the last value of D.
• The truth table for D flip flop is as given below.

Or 1
JK Flip Flop

• One of the most useful and versatile flip flop is the JK flip flop.
• Features of a JK flip flop are:
1. If the J and K input are both at 1 and the clock pulse is applied, then
the output will change state, regardless of its previous condition.
2. If both J and K inputs are at 0 and the clock pulse is applied there will
be no change in the output.
3. There is no indeterminate condition in the operation of JK flip flop like
SR flip flop ) i.e. it has no ambiguous state.
JK flip-flop is named after Jack Kilby, an electrical engineer who invented
IC.
• When J is HIGH and K is LOW, the Q output goes HIGH on the triggering edge
of the clock pulse, and the flip-flop is SET.
• When J is LOW and K is HIGH, the Q output goes LOW on the triggering edge
of the clock pulse, and the flip-flop is RESET.
• When both J and K are LOW, the output does not change from its prior state.
• When J and K are both HIGH, the flip-flop changes state. This called the
toggle mode.
(A JK flip-flop is a modification of SR flip-flop. In this the J input is similar to the
set input of SR flip-flop and the K input is similar to the reset input of SR flip-
flop.
The condition J = K = 1 which is not allowed in SR flip-flop (S = R = 1) is
interpreted as a toggle command.)
Race Around Condition In JK Flip-flop – 

For J-K flip-flop, if J=K=1, and if clk=1 for a long period of time, then Q
output will toggle as long as CLK is high, which makes the output of the
flip-flop unstable or uncertain.
This problem is called race around condition in J-K flip-flop. This problem
can be avoided by using  JK flip flop in Master slave configuration.
MASTER-SLAVE JK FLIP FLOP
The Master-Slave Flip-Flop is basically a combination of two JK flip-flops
connected together in a series configuration.
Out of these, one acts as the “master” and the other as a “slave”.
The output from the master flip flop is connected to the two inputs of the
slave flip flop whose output is fed back to inputs of the master flip flop.
In addition to these two flip-flops, the circuit also includes an inverter.
The inverter is connected to clock pulse in such a way that the inverted clock
pulse is given to the slave flip-flop.
In other words if CP=0 for a master flip-flop, then CP=1 for a slave flip-flop
and if CP=1 for master flip flop then it becomes 0 for slave flip flop.
(i.e. when master is active slave is inactive and vice-versa).
 Working of a JK master slave flip flop :
• When the clock pulse goes to 1, master is activated and the slave is isolated;
• The slave flip-flop is isolated until the CP goes to 0. When the CP goes back to 0,
information is passed from the master flip-flop to the slave and output is obtained.
• If J=0 and K=1, the high Q’ output of the master goes to the K input of the slave
and the clock forces the slave to reset, thus the slave copies the master.
• If J=1 and K=0, the high Q output of the master goes to the J input of the slave and
the Negative transition of the clock sets the slave, copying the master.
• If J=1 and K=1, it toggles on the positive transition of the clock and the slave copies
it when the clock is zero.
• If J=0 and K=0, Q remains unchanged.
• Slave always follows the master. ( i.e output of slave is same as the output of
master).
Waveforms
SR master slave flip flop
• This circuit consists of two S-R FFs in master-slave configuration.
• First flip flop operates as the master, while the second flip flop is slaved
to the master.
• Its truth table is same as that of a clocked SR FF.
• The two inputs S and R are used to set and reset the data respectively.
The clock input CLK is used to control both the master and slave FFs
making sure only one of the FFs operates at any given time.
• By going to a master-slave structure, We have given plenty of time for
the master FF to respond to the input signals, and for those input
signals to change and settle following the previous change of state.
Applications of FF
FFs are extensively used in the following sequential logic circuits:
• Counters
• Registers / shift registers
• Frequency Dividers
• Data transfer
Flip Flop – Triggering Methods