LATCHES & FLIP

FLOPS
Latches and flip flops are memory
devices used in the
construction of Sequential circuits
LATCH BLOCK DIAGRAM
FLIP FLOP BLOCK DIAGRAM
FLIP FLOPS
★ A flip flop is an electronic circuit with two stable states
that can be used to store binary data.
★ The stored data can be changed by applying varying
inputs.
★ Flip-flops and latches are fundamental building blocks of
digital electronics systems used in computers,
communications, and many other types of systems.
★ Flip-flops and latches are used as data storage elements.
DIFFERENCE BETWEEN LATCHES AND FLIP FLOPS

➢ The main difference between latch and flip

flop is that the latch checks the input
continuously and changes the output when
there is a change in the input.
Flip Flop

➢ The latches with the clock signal

provided are known as Flip-Flops.
➢ Output of a Flip Flop changes with
input (respond to the input) only when
the clock is present
 SR FLIP FLOP

⮚ It has two inputs

⮚one which will “Set” the device (i.e.
the output is 1), and is labelled S
⮚ other which will “Reset” the device
(i.e. the output is 0), labelled R.

⮚The name SR stands for “ Set-Reset”

S R FLIP FLOP
S R FLIP FLOP
JK FLIP FLOP
 J K Flip Flop
⮚ JK flip flop is a refined & improved version of
SR Flip Flop that has been introduced to solve
the problem of indeterminate state that occurs
in SR flip flop when both the inputs are 1.
BLOCK DIAGRAM OF JK FLIP FLOP
JK Flip Flop

⮚Jack Kilby, a Texas instrument engineer who invented IC.

⮚Input J behaves like input S of SR flip flop which was
meant to set the flip flop.
⮚Input K behaves like input R of SR flip flop which was
meant to reset the flip flop.
When J=K=0
⮚ When both J and K are 0, the clock pulse has no effect
on the output and the output of flip-flop is same as its
previous value.
⮚ This is because when both the J and K are 0, the output
of their respective AND gate becomes 0.
When J=0, K=1
❖When J=0, the output of the AND gate corresponding to J
becomes 0(i.e.) S=0 and R=1.
❖Therefore Q’ becomes 0.
❖This condition will reset the flip-flop. This represents the
RESET state of Flip-flop.
When J=1, K=0
❑In this case, the AND gate corresponding to K becomes
0(i.e.) S=1 and R=0.
❑Therefore Q becomes 0.
❑This condition will set the Flip-flop.
❑This represents the SET state of Flip-flop.
When J=K=1
⮚ Consider the condition when CP=1 and J=K=1.
⮚ This condition will cause the output to complement again
and again.
⮚ This complement operation continues until the Clock
pulse goes back to 0.
⮚ This condition is called Toggle condition
✔Since this condition is undesirable, we have to find a way
to eliminate this condition.
✔This undesirable behaviour can be eliminated by Edge
triggering of JK flip-flop or by using master slave JK Flip-
flops.
TRUTH TABLE OF JK FLIP FLOP