De Unit3 Slides

DIGITAL ELECTRONICS
GAYATHRI DEVI B
Department of Electrical & Electronics Engineering

DIGITAL ELECTRONICS
Flip Flops & Applications
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Latches
What is Latch?
❖ Latch is an electronic device, which changes its output
immediately based on the applied input. It is used to store
either 1 or 0 at any specified time.
❖ It consists of two inputs namely “SET” and RESET and two

outputs, which are complement to each other.
What are Latches and Flip Flops?

❖ Generally, the latches and flip-flops can be used to store one
bit of data in the bit format. These are the building blocks
and works like basic elements in computers, electronic
systems, etc.
DIGITAL ELECTRONICS
Latches
❖ The major difference between latches & FFs is that a latch

verifies the i/p constantly and alters the output based on the
input change.
❖ whereas a FF is a blend of the latch as well as a clock, it

checks the input & modifies the time of output which is
attuned by the CLK (clock).
DIGITAL ELECTRONICS
Latches
DIGITAL ELECTRONICS
Latches
Types of Latches:
1. RS LATCH USING NOR GATES
2. S’R’ LATCH USING NAND GATES

DIGITAL ELECTRONICS
Latches
RS LATCH USING NOR GATES
SR flip flop can also be designed by cross coupling of two NOR

gates. It is an active high input SR flip – flop.
DIGITAL ELECTRONICS
Latches
Working:
Case 1:When R=S=0

When both the SET and RESET inputs are low, then the output
remains in previous state i.e. it holds the previous data.
DIGITAL ELECTRONICS
Latches
Case 2: When S=0 & R=1
❖ When SET input is low and RESET input is high, then the flip
flop will be in RESET state.
❖ Because the high input of NOR gate with R input drives the
other NOR gate with 0, as its output is 0.
❖ So both the inputs of the NOR gate with S input are 0. This
will cause the output of the flip – flop to settle in RESET
state.
DIGITAL ELECTRONICS
Latches
❖ When SET input is high and RESET input is low, then the flip
flop will be in SET state.
❖ Because the low input of NOR gate with S input drives the
other NOR gate with 1, as its output is 1.
❖ So both the inputs of the NOR gate with R input are 1. This
will cause the output of the flip flop to settle in SET state.
DIGITAL ELECTRONICS
Latches
❖ When both the SET and RESET inputs are high, then the flip
flop will be undefined state.
❖ Because the high inputs of S and R, violates the rule of flip

flop that the outputs should complement to each other. So
the flip flop is in undefined state (or forbidden state).
❖ The table below summarizes above explained working of SR

Flip Flop designed with the help of a NOR gate.
DIGITAL ELECTRONICS
Latches
S’R’ LATCH USING NAND GATES

DIGITAL ELECTRONICS
Latches
Working:
❖ When both the SET and RESET inputs are high, then the
output remains in previous state i.e. it holds the previous
data.
❖ When SET input is HIGH and RESET input is LOW, then the
flip flop will be in RESET state.
❖ Because the low input of NAND gate with R input drives the
other NAND gate with 1, as its output is 1.
❖ So both the inputs of the NAND gate with S input are 1.

This will cause the output of the flip – flop to settle in
RESET state.
DIGITAL ELECTRONICS
Latches
❖ When SET input is LOW and RESET input is HIGH, then the flip
flop will be in SET state.
❖ Because the low input of NAND gate with S input drives the
other NAND gate with 1, as its output is 1.
❖ So both the inputs of the NAND gate with R input are 1. This
will cause the output of the flip – flop to settle in SET state.
DIGITAL ELECTRONICS
Latches
❖ When both the SET and RESET inputs are low, then the flip flop
will be in undefined state.
❖ Because the low inputs of S and R, violates the rule of flip – flop
that the outputs should compliment to each other.
❖ So the flip flop is in undefined state (or forbidden state).

DIGITAL ELECTRONICS
Latches
RS/S’R’ Latches as Switch Debouncers

What is switch Bouncing?
❖ Mechanical switches, when pressed or released, often take
some time and vibrate several times before settling down.
❖ This non – ideal behavior of the switch is called switch bounce

or mechanical bounce. This mechanical bounce will tend to
fluctuate between low and high voltages which can be
interpreted by digital circuit.
❖ This can result in variation of pulse signals and these series of

unwanted pulses will result in the digital system to work
incorrectly.
DIGITAL ELECTRONICS
Latches
❖ We use switch in our day to day life to switch ON/OFF a bulb

or a fan or any electrical devices. But when we use switches
in digital circuits, we observe a phenomenon called
bouncing.
❖ This occurs because, when we turn the switch, the

mechanical parts vibrate. i.e It toggles between ON and OFF
state for some time until the mechanical contact attain
equilibrium. this vibrations are minute and are not at all
noticeable in electrical circuit.
❖ where as in digital circuits, these vibrations create pulses.
which are detected by circuits which results in an error.
DIGITAL ELECTRONICS
Latches
From the timing diagram it is evident that there are several

unwanted pulses which are present due to bouncing. This can
be eliminated by using SR latch using NOR gates and NAND
gates.
DIGITAL ELECTRONICS
Latches
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GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Flip Flops
❖ Flip-flop is a basic digital memory circuit, which stores one

bit of information.Flip flops are the fundamental blocks of
most sequential circuits.
❖ It is also known as a bistable multivibrator or a binary or

one-bit memory. Flip-flops are used as memory elements in
sequential circuit.
DIGITAL ELECTRONICS
Flip Flops
Classification of Flip-Flops
1.Level Triggered FFs:
Generally, latches belong to this category.
The FF is triggered at levels of the clock pulse(either 1 or 0 level)
2. Edge Triggered FFs:
• The FF changes the state either at the positive/rising edge or at
negative/falling edge of the clock pulse on a control input(CLK)
• If the FF is triggered at rising edge of the CLK, then it’s a
positive edge triggered FF.
• If the FF is triggered at falling edge of the CLK, then it’s a
neegative edge triggered FF.
DIGITAL ELECTRONICS
Flip Flops
❖If the data inputs are transferred to FF outputs only on the
triggering edge of the CLK and is Dependent on CLK , then they
are said to be synchronous inputs.
❖If there are PRESET(PR) and CLEAR(CLR), they affect the state of
the FF and is INDEPENDENT of CLK, then PR and CLR are said to
be asynchronous inputs.
DIGITAL ELECTRONICS
Flip Flops
❖Types of positive edge triggered flip – flops (Synchronous

Inputs)
1. Set-Reset/SR Flip-Flop
2. JK Flip-Flop
3. Data/D Flip-Flop
4. Toggle/T Flip-Flop
DIGITAL ELECTRONICS
Flip Flops
1. SR Flip-Flop:
DIGITAL ELECTRONICS
Flip Flops
❖From the truth table of SR Flip-Flop, we observe that when

S=R=1
The output is unpredictable/indeterminate. Hence the output is
said be Forbidden state represented by ‘-’.
➢This is because both the output of NAND gate will try to change
the output state depending on the propagation delay and creates
race around problem.
➢The NAND gate which wins the race among the two will retain the
state and other will have complimented state.
DIGITAL ELECTRONICS
Flip Flops
2.JK Flip-Flop:
DIGITAL ELECTRONICS
Flip Flops
❖It works similar to SR FF. The only difference is that there is no

indeterminant/forbidden/unpredictable state.
❖When both J=K=1, the output toggles.
Toggling is changing of output of the flip flop to opposite States

for application of each CLOCK /TRIGGER input.
DIGITAL ELECTRONICS
Flip Flops
3. Data Flip-Flop.
TRUTH TABLE
DIGITAL ELECTRONICS
Flip Flops
❖Data FF is used in memory chips to store bits of data.
❖Preferably can be used in the design of Shift Registers.

DIGITAL ELECTRONICS
Flip Flops
4. Toggle Flip-Flop:
TRUTH TABLE
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GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Characteristic Equations of F/Fs
❖Characteristic equation gives the next state equation of a given

flip-flop with the given inputs and present state.
❖To derive the characteristic equation of a FF, write the function

table of the given FF and construct K-Map with the given inputs
and present state determine the equation of the next state.
DIGITAL ELECTRONICS
1. SR Flip Flop Characteristic Equation:

The Next State table is given by;
CLK S R Qn (present Q n+1 (next

state) state)
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 FORBIDDEN
1 1 1 0 FORBIDDEN
DIGITAL ELECTRONICS
K-Map to determine Q n+1
The Next State Equation is Q n+1 = S+R’Q

DIGITAL ELECTRONICS
2. JK Flip-Flop Characteristic Equation:

CLK J K Qn Q n+1
1 0 0 0 0
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 1
1 1 0 1 1
1 1 1 0 1
1 1 1 1 0
DIGITAL ELECTRONICS
The Next State Equation is Q n+1 = JQ’+K’Q

DIGITAL ELECTRONICS
3. Data Flip-Flop Characteristic Equation:

CLK D Qn Q n+1
1 0 0 0
1 0 1 0
1 1 0 1
1 1 1 1
DIGITAL ELECTRONICS

D Q Q’ Q
D’ 0 0
D 1 1
D
The Next State Equation is Q n+1 = D
DIGITAL ELECTRONICS
4. Toggle Flip-Flop Characteristic Equation:
CLK T Qn Q n+1
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0
DIGITAL ELECTRONICS
The Next State Equation is Q n+1 = TQ’+T’Q= T EXOR Q

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DIGITAL ELECTRONICS
GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Application Tables of F/Fs
Why Application Tables ?
❖ Application Tables will help in designing Synchronous

Counters in connecting combinatinal logic to inputs of the
F/Fs in order to excite the f/fs to get required pattern.
❖ With the knowledge of basic functioning of F/F, one can write

the Application Table of the same.
DIGITAL ELECTRONICS
Application Table of S R F/F:
Function Table of S R F/F is as follows;

CLOCK S R Q Q’
X X NO CHANGE
0
0 0 NO CHANGE
1
0 1 0 1 (RESET)
1
1 0 1 0(SET)
1
1 1 FORBIDDEN(INVALID)
1
DIGITAL ELECTRONICS
Q Q+ S R
0 0 0 X
0 1 1 0
1 0 0 1
1 X 0
1
DIGITAL ELECTRONICS
Application Table of J K F/F:
Function Table of J K F/F is as follows;

CLOCK J K Q Q’
X X NO CHANGE
0
0 0 NO CHANGE
1
0 1 0 1 (RESET)
1
1 0 1 0(SET)
1
1 1 TOGGLING
1
DIGITAL ELECTRONICS
Q Q+ J K
0 0 0 X
0 1 1 X
1 0 X 1
1 X 0
1
DIGITAL ELECTRONICS
Application Table of D F/F:
Function Table of D F/F is as follows;

CLOCK D Q Q’
0 X NO CHANGE
1 0 0 1
1 1 1 0
DIGITAL ELECTRONICS
Q Q+ D
0 0 0
0 1 1
1 0 0
1 1
1
DIGITAL ELECTRONICS
Application Table of T F/F:
Function Table of T F/F is as follows;

CLOCK T Q Q’
0 X NO CHANGE
NO CHANGE
1 0
TOGGLING
1 1
DIGITAL ELECTRONICS
Q Q+ T
0 0 0
0 1 1
1 0 1
1 0
1
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GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖ Edge triggered clocked F/Fs are used in

1. Shift registers- to transfer the stored data serially or parallely.
2. Binary Counters
3. Event detection
4. Frequency Dividers
5. Finite State Machines(FSMs)
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖A F/F stores single bit of binary data either 1 or 0.
❖If multiple F/Fs are connected to store multiple bits of data, then
it’s a register.
❖Shift register store the data and the stored data is moved in /out
of the register using clock pulses.
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖Serial type of shift register is the one where the data is transfer
one bit after the other.
❖Parallel type of shift register is one in which data is given to each

F/F seperately in simultaneous manner.
DIGITAL ELECTRONICS
SHIFT REGISTERS
Classification of Shift Register
Based on Inputting Data and Retrieving Data,Shift Registers can be
classified as
1. Serial In Serial Out SR(SISO)
2. Serial In Parallel Out SR(SIPO)
3. Parallel In Serial Out SR(PISO)
4. Parallel In Parallel Out(PIPO)

DIGITAL ELECTRONICS
SHIFT REGISTERS
1. SISO :
❖The shift register, which allows serial input (one bit after the
other through a single data line) and produces a serial output is
known as Serial-In Serial-Out shift register. Since there is only one
output, the data leaves the shift register one bit at a time in a
serial pattern, thus the name Serial-In Serial-Out Shift Register.
❖A 4 bit SISO SR is shown here.
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖The circuit consists of four D flip-flops which are connected in a

serial manner.
❖All these flip-flops are synchronous with each other since the
same clock signal is applied to each flip flop.
DIGITAL ELECTRONICS
SHIFT REGISTERS
2. SIPO
❖The shift register, which allows serial input (one bit after the
other through a single data line) and produces a parallel output
is known as Serial-In Parallel-Out shift register.
❖A 4 bit SIPO SR is shown here.
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖The clear (CLR) signal is connected in addition to the clock
signal to all the 4 flip flops in order to RESET them.
❖The output of the first flip flop is connected to the input of the
next flip flop and so on. All these flip-flops are synchronous
with each other since the same clock signal is applied to each
flip flop.
DIGITAL ELECTRONICS
SHIFT REGISTERS
3. PISO
❖The shift register, which allows parallel input (data is given
separately to each flip flop and in a simultaneous manner) and
produces a serial output is known as Parallel-In Serial-Out shift
register.
❖A 4 bit PISO SR is shown here.
DIGITAL ELECTRONICS- UE19EE203
SHIFT REGISTERS
❖The circuit consists of four D flip-flops which are connected
through external combinational logic.
❖The clock input is directly connected to all the flip flops but the
input data is connected individually to each flip flop through a
multiplexer at the input of every flip flop.
❖The output of the previous flip flop and parallel data input are
connected to the input of the MUX and the output of MUX is
connected to the next flip flop.
❖All these flip-flops are synchronous with each other since the
same clock signal is applied to each flip flop.
DIGITAL ELECTRONICS
SHIFT REGISTERS
4. PIPO
❖The shift register, which allows parallel input (data is given
separately to each flip flop and in a simultaneous manner) and
also produces a parallel output is known as Parallel-In parallel-
Out shift register.
❖A 4 bit PIPO SR is shown here.
DIGITAL ELECTRONICS
SHIFT REGISTERS
❖The circuit consists of four D flip-flops which are connected. The

clear (CLR) signal and clock signals are connected to all the 4 flip
flops.
❖In this type of register, there are no interconnections between

the individual flip-flops since no serial shifting of the data is
required.
❖Data is given as input separately for each flip flop and in the
same way, output also collected individually from each flip flop.
DIGITAL ELECTRONICS
SHIFT REGISTERS
Universal Shift Registers

❖A Universal shift register is a register which has both the right
shift and left shift with parallel load capabilities.
❖Universal shift registers are used as memory elements in

computers.
❖The Universal shift register is a combination design

of bidirectional shift register and a unidirectional shift register
with parallel load provision.
DIGITAL ELECTRONICS
SHIFT REGISTERS
DIGITAL ELECTRONICS
SHIFT REGISTERS
Basic connections –Universal SR

❖The first input (zeroth pin of multiplexer) is connected to the
output pin of the corresponding flip-flop.
❖The second input (first pin of multiplexer) is connected to the
output of the very-previous flip flop which facilitates the right
shift.
❖The third input (second pin of multiplexer) is connected to the
output of the very-next flip-flop which facilitates the left shift.
❖The fourth input (third pin of multiplexer) is connected to the
individual bits of the input data which facilitates parallel
loading.
DIGITAL ELECTRONICS
SHIFT REGISTERS
Working of Universal Shift Register depends on the inputs given to

the select lines.
S1 S0 REGISTER OPERATION
0 0 NO CHANGE
0 1 SHIFT RIGHT
1 0 SHIFT LEFT
1 1 PARALLEL LOAD
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GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
COUNTERS-Introduction
❖ Counter is a device which stores (and sometimes displays) the

number of times a particular event or process has occurred,
often in relation to a clock signal.
❖Counters are also referred as PATTERN GENERATORS
❖Counter is a sequential circuit. A digital circuit which is used for

a counting pulses is known counter.
❖Counter is the widest application of flip-flops. It is a group of

flip-flops with a clock signal applied.
DIGITAL ELECTRONICS
COUNTERS-Introduction
Counters are broadly divided into two categories;

❖Asynchronous counter
❖Synchronous counter
❖ The Asynchronous counter is also known as the ripple
counter.
❖ In asynchronous counter we don’t use universal clock, only first

flip flop is driven by main clock and the clock input of rest of the
following flip flop is driven by output of previous flip flops
DIGITAL ELECTRONICS
RIPPLE COUNTERS
❖ In a ripple counter the clock input has to propagate through

each flip-flop of the counter.
❖ A ripple counter is also called an asynchronous counter because

each flip-flop does not change at the same time.
❖ The propagation delay of each flip-flop adds together to give a

total propagation delay for the counter.
DIGITAL ELECTRONICS
RIPPLE COUNTERS
2-bit Asychronous Counter using –ve Edge Triggered F/Fs.
❖ Below is a diagram of the 2-bit Asynchronous counter in which
we used two T flip-flops. Apart from the T flip flop, we can also
use the JK flip flop by setting both of the inputs to 1
permanently. The external clock pass to the clock input of the
first flip flop, i.e., FF-A and its output, i.e., is passed to clock
input of the next flip flop, i.e., FF-B.
DIGITAL ELECTRONICS
RIPPLE COUNTERS
Timing Diagram of 2-bit Ripple Counter

DIGITAL ELECTRONICS
RIPPLE COUNTERS
Analysis of 2-bit Ripple Counter

Condition 1: When both the flip flops are in reset condition.
Operation: The outputs of both flip flops, i.e., QA QB, will be 0.
Condition 2: When the first negative clock edge passes.
Operation: The first flip flop will toggle, and the output of this flip
flop will change from 0 to 1. The output of this flip flop will be taken
by the clock input of the next flip flop. This output will be taken as a
positive edge clock by the second flip flop. This input will not
change the second flip flop's output state because it is the negative
edge triggered flip flop.So, QA = 1 and QB = 0.
DIGITAL ELECTRONICS
RIPPLE COUNTERS
Analysis of 2-bit Ripple Counter

Condition 3: When the second negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of this
flip flop will change from 1 to 0. This output will be taken as a
negative edge clock by the second flip flop. This input will change
the second flip flop's output state because it is the negative edge
triggered flip flop.So, QA = 0 and QB = 1.
Condition 4: When the third negative clock edge is applied.

Operation: The first flip flop will toggle again, and the output of this
flip flop will change from 0 to 1. This output will be taken as a
positive edge clock by the second flip flop. This input will not
change the second flip flop's output state because it is the negative
edge triggered flip flop.So, QA = 1 and QB = 1
DIGITAL ELECTRONICS
RIPPLE COUNTERS
Condition 5: When the fourth negative clock edge is applied.
Operation: The first flip flop will toggle again, and the output of
this flip flop will change from 1 to 0.
This output will be taken as a negative edge clock by the second

flip flop. This input will change the output state of the second flip
flop.So, QA = 0 and QB = 0
DIGITAL ELECTRONICS
Decade Counters
Decade Counter
• A decade counter counts ten different states and then reset to
its initial states. A simple decade counter will count from 0 to 9.
DIGITAL ELECTRONICS
Decade Counters
CLOCK Q3 Q2 Q1 Q0
PULSE
0 0 0 0 0
1 0 0 0 1
2 0 0 1 0
3 0 0 1 1
4 0 1 0 0
5 0 1 0 1
6 0 1 1 0
7 0 1 1 1
8 1 0 0 0
9 1 0 0 1
10 0 0 0 0
Ripple Counters
❖A n-bit ripple counter can count up to 2n states.
❖It is known as ripple counter because of the way the clock

pulse ripples its way through the flip-flops.
DIGITAL ELECTRONICS
Ripple Counters
A 3-bit Ripple Counter using JK F/F

DIGITAL ELECTRONICS
Ripple Counters
DIGITAL ELECTRONICS
Ripple Counters
❖The 3-bit ripple counter used in the circuit above has eight
different states, each one of which represents a count value.
❖Similarly, a counter having n flip-flops can have a maximum of 2
to the power n states. The number of states that a counter owns
is known as its mod (modulo) number. Hence a 3-bit counter is a
mod-8 counter.
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DIGITAL ELECTRONICS
Synchronous Binary Counters
What is a Synchronous Counter?

❖ A synchronous counter, in contrast to an asynchronous
counter, is one whose output bits change state
simultaneously, with no ripple.
❖ The only way we can build such a counter circuit from J-K
flip-flops is to connect all the clock inputs together, so that
each and every flip-flop receives the exact same clock pulse
at the exact same time:
DIGITAL ELECTRONICS
❖ Synchronous Counters are so called because the clock input of

all the individual flip-flops within the counter are all clocked
together at the same time by the same clock signal
DIGITAL ELECTRONICS
Triggering A Synchronous Counter

Synchronous Counters use edge-triggered flip-flops that change
states on either the “positive-edge” (rising edge) or the
“negative-edge” (falling edge) of the clock pulse on the control
input resulting in one single count when the clock input changes
state.
DIGITAL ELECTRONICS
❖ It may seem unusual that ripple counters use the falling-edge

of the clock cycle to change state, but this makes it easier to
link counters together because the most significant bit (MSB) of
one counter can drive the clock input of the next.
❖ This works because the next bit must change state when the
previous bit changes from high to low – the point at which a
carry must occur to the next bit. Synchronous counters usually
have a carry-out and a carry-in pin for linking counters together
without introducing any propagation delays.
DIGITAL ELECTRONICS
What is a Mod n counter?

❖ Mod n or Modulus of n, is a way of referring to the maximum
count of a counter. Every counter has a limit with regards to
the number they can count up or down to. Mod n expresses
that limit.
❖ It is an important label for a counter because it gives us the

maximum count of the counter, as well as the number of flip-
flops present in the counter.
❖ A mod n counter can count up to n events.

DIGITAL ELECTRONICS
Different types of Synchronous Counters

There are many types of synchronous counters available in
digital electronics. They are listed below.
❖ Binary counters
❖ 4 bit synchronous UP counter
❖ 4 bit synchronous DOWN counter
❖ 4 bit synchronous UP / DOWN counter
❖ Loadable counters
❖ BCD counters
❖ Ring counters
❖ Johnson counters etc.
DIGITAL ELECTRONICS
Advantages and Disadvantage of Synchronous Counter

The advantages of the Synchronous counter is as follows-
1.It’s easier to design than the Asynchronous counter.
2.It acts simultaneously.
3.No propagation delay associated with it.
4.Count sequence is controlled using logic gates, error chances
are lower.
5.Faster operation than the Asynchronous counter.
Although there are many advantages, one

major disadvantage of working with Synchronous counter is
that it requires a lot of extra logic to perform.
DIGITAL ELECTRONICS
Use of Synchronous Counter

Few applications where Synchronous counters are used-
1.Machine Motion control
2.Motor RPM counter
3.Rotary Shaft Encoders
4.Digital clock or pulse generators.
5.Digital Watch and Alarm systems.
DIGITAL ELECTRONICS
Synchronous Counter Summary
Then to summarise some of the main points about Synchronous
Counters:
•Synchronous Counters can be made from Toggle or D-type flip-
flops.
•Synchronous counters are easier to design than asynchronous
counters.
•They are called synchronous counters because the clock input
of the flip-flops
are all clocked together at the same time with the same clock
signal.
•Due to this common clock pulse all output states switch or
change simultaneously.
DIGITAL ELECTRONICS
•With all clock inputs wired together there is no inherent
propagation delay.
•Synchronous counters are sometimes called parallel counters as
the clock is fed in parallel to all flip-flops.
•The inherent memory circuit keeps track of the counters
present state.
•The count sequence is controlled using logic gates.
•Overall faster operation may be achieved compared to
Asynchronous counters.
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DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Design of Synchronous Counters
Design counter for given sequence

Problem – Design synchronous counter for sequence: 0 → 1 →
3 → 4 → 5 → 7 → 0, using T flip-flop.
Explanation – For given sequence, state transition diagram as
following below:
DIGITAL ELECTRONICS
Design of Counters
State transition table for given sequence:
PRESENT STATE NEXT STATE
Q3 Q2 Q1 Q3(t+1) Q2(t+1) Q1(t+1)
0 0 0 0 0 1
0 0 1 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 1 0 0 0
DIGITAL ELECTRONICS
Design of Counters
T flip-flop – If value of Q changes either from 0 to 1 or from 1

to 0 then input for T flip-flop is 1 else input value is 0.
QT QT+1 T
0 0 0
0 1 1
1 0 1
1 1 0
DIGITAL ELECTRONICS
Design of Counters
Draw input table of all T flip-flops by using the excitation table of

T flip-flop. As nature of T flip-flop is toggle in nature. Here, Q3 as
Most significant bit and Q1 as least significant bit.
INPUT TABLE OF FLIP-FLOPS
T3 T2 T1
0 0 1
0 1 0
1 1 1
0 0 1
0 1 0
1 1 1
DIGITAL ELECTRONICS
Design of Counters
Find value of T3, T2, T1 in terms of Q3, Q2, Q1 using K-Map

(Karnaugh Map):
Therefore,T3 = Q2
DIGITAL ELECTRONICS
Design of Counters
T2 = Q1 + Q2
DIGITAL ELECTRONICS
Design of Counters
T1 = Q2’
DIGITAL ELECTRONICS
Design of Counters
Now, you can design required circuit using expressions of K-maps:

DIGITAL ELECTRONICS
Design of Counters
SYNCHRONOUS COUNTER DESIGN STEPS/PROCEDURES

1. Determine the # of FFs needed to support the counting
sequence’s
highest #.
2n -1 ≥ Highest #
2. Build a State Transition Diagram. Be sure to include all states.
3. Build a State/Excitation Truth Table.
4. Simplify expressions for J and K inputs for each F/F on K-Maps.
5. Implement the Synchronous Counter/State Machine Circuit.
6. Draw the Timing Diagram (If Needed).
THANK YOU
Gayathri Devi B
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS
GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Design of Counters
Design synchronous counter to count the sequence 0-1-2-3-4-

5-0
Step1: Determine the desired number of FFs From the given
sequence the number of FFs is equal to 3.
Step2: Write the excitation table and circuit excitation
table Table1 shows the excitation table for JK flip flop.
DIGITAL ELECTRONICS
Design of Counters
DIGITAL ELECTRONICS
Design of Counters
Step 4: K-maps and simplification

DIGITAL ELECTRONICS
Design of Counters
DIGITAL ELECTRONICS
Design of Counters
Step5: Logic diagram

DIGITAL ELECTRONICS
Design of Counters
HOME WORK:
Design a counter that counts in the sequence: 101, 100, 011, 010,
001, 000, 101, ... Use clocked D flip-flops. Draw the circuit
diagram. What will happen if your counter starts in an invalid
state?
THANK YOU
Gayathri Devi B
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS
GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Shift Register Based Counters
Shift Register Counter
❖Shift Register Counters are the shift registers in which the

outputs are connected back to the inputs in order to produce
particular sequences. These are basically of two types:
Ring Counter
❖A ring counter is basically a shift register counter in which the
output of the first flip flop is connected to the next flip flop
and so on and the output of the last flip flop is again fed back
to the input of the first flip flop, thus the name ring counter.
The data pattern within the shift register will circulate as long
as clock pulses are applied.
DIGITAL ELECTRONICS
❖The logic circuit given below shows a Ring Counter. The circuit
consists of four D flip-flops which are connected. Since the
circuit consists of four flip flops the data pattern will repeat
after every four clock pulses as shown in the truth table below:
DIGITAL ELECTRONICS
❖ A Ring counter is generally used because it is self-decoding. No extra

decoding circuit is needed to determine what state the counter is in.
DIGITAL ELECTRONICS
Johnson Counter
❖ A Johnson counter is basically a shift register counter in which
the output of the first flip flop is connected to the next flip flop
and so on and the inverted output of the last flip flop is again
fed back to the input of the first flip flop.
❖ They are also known as twisted ring counters.The logic circuit

given below shows a Johnson Counter. The circuit consists of
four D flip-flops which are connected.
❖ An n-stage Johnson counter yields a count sequence of 2n

different states, thus also known as a mod-2n counter. Since the
circuit consists of four flip flops the data pattern will repeat
every eight clock pulses as shown in the truth table below:
DIGITAL ELECTRONICS
DIGITAL ELECTRONICS
The main advantage of Johnson counter is that it only needs n

number of flip-flops compared to the ring counter to circulate a
given data to generate a sequence of 2n states.
DIGITAL ELECTRONICS
❖ Johnson counter also known as creeping counter, is an

example of synchronous counter.
❖ In Johnson counter, the complemented output of last flip

flop is connected to input of first flip flop and to implement
n-bit Johnson counter we require n flip-flop.
❖ It is one of the most important type of shift register counter.

It is formed by the feedback of the output to its own input.
❖ Johnson counter is a ring with an inversion.Another name of

Johnson counter are:creeping counter, twisted ring counter,
walking counter, mobile counter and switch tail counter.
DIGITAL ELECTRONICS
Example:
If n=4
4-bit Johnson counter
Initially, suppose all flip-flops are reset.
DIGITAL ELECTRONICS
DIGITAL ELECTRONICS
where,
CP is clock pulse and
Q1, Q2, Q3, Q4 are the states.
Question: Determine the total number of used and unused
states in 4-bit Johnson counter.
Answer: Total number of used states= 2*n
= 2*4
=8
Total number of unused states= 2n – 2*n
= 24-2*4
=8
DIGITAL ELECTRONICS
Advantages of Johnson counter:

•The Johnson counter has same number of flip flop but it can
count twice the number of states the ring counter can count.
•It can be implemented using D and JK flip flop.
•Johnson ring counter is used to count the data in a continuous
loop.
•Johnson counter is a self-decoding circuit.
Disadvantages of Johnson counter:
•Johnson counter doesn’t count in a binary sequence.
•In Johnson counter more number of states remain unutilized
than the number of states being utilized.
•The number of flip flops needed is one half the number of
timing signals.
•It can be constructed for any number of timing sequence.
DIGITAL ELECTRONICS
Applications of Johnson counter:

❖ Johnson counter is used as a synchronous decade counter or
divider circuit.
❖ It is used in hardware logic design to create complicated

Finite states machine. ex: ASIC and FPGA design.
❖ The 3 stage Johnson counter is used as a 3 phase square wave

generator which produces 1200 phase shift.
❖ It is used to divide the frequency of the clock signal by

varrying their feedback.
THANK YOU
Gayathri Devi B
gayathridb@pes.edu
+91 80 6666 3333 Extn 273
DIGITAL ELECTRONICS
GAYATHRI DEVI B

DIGITAL ELECTRONICS
GAYATHRI DEVI B
DIGITAL ELECTRONICS
Conversion of F/Fs
Conversion of JK to T F/F:
Step 1:
Write the function table of T F/F
T Qn Q n+1
0 0 0
1 0 1
0 1 0
0 1 1
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 2:
Write the application table of J K F/F.
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 3:
Write the Overall Excitation Table.
T Qn Qn+1 J K
0 0 0 0 X
1 0 1 1 X
1 1 0 X 1
0 1 1 X 0
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 4:
Write K-Map for determining expression for J, K in terms of T.
T Qn Qn’ Qn
T’ 0 X
T 1 X
J=T
T Qn Qn’ Qn
T’ X 0
T X 1
K=T
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 5:
Write the Implementation diagram.
DIGITAL ELECTRONICS
Conversion of F/Fs
Conversion of JK to D F/F
Step 1:
D Qn Qn+1
0 0 0
0 1 0
1 0 1
1 1 1
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 2:
Qn Qn+1 J Q
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 3:
D Qn Qn+1 J K
0 0 0 0 X
1 0 1 1 X
0 1 0 X 1
1 1 1 X 0
Conversion of F/Fs
Step 4:
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 5:
DIGITAL ELECTRONICS
Conversion of F/Fs
Conversion of JK to SR F/F:
Step 1:
S R Qn Qn+1
0 0 X X
0 1 X 0
1 0 X 1
1 1 -- --
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 2:
Qn Qn+1 J K
0 0 0 X
0 1 1 X
1 0 X 1
1 1 X 0
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 3:
S R Qn Qn+1 J K
0 0 0 0 0 X
0 0 1 1 X 0
0 1 0 0 0 X
0 1 1 0 X 1
1 0 0 1 1 X
1 0 1 1 X 0
1 1 0 FORBIDDEN X X
1 1 1 FORBIDDEN X X
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 4:
DIGITAL ELECTRONICS
Conversion of F/Fs
Step 5:
THANK YOU
Gayathri Devi B
gayathridb@pes.edu
+91 80 6666 3333 Extn 273

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Department of Electrical & Electronics Engineering

Flip Flops & Applications

❖ It consists of two inputs namely “SET” and RESET and two

What are Latches and Flip Flops?

❖ The major difference between latches & FFs is that a latch

❖ whereas a FF is a blend of the latch as well as a clock, it

1. RS LATCH USING NOR GATES

2. S’R’ LATCH USING NAND GATES

RS LATCH USING NOR GATES

SR flip flop can also be designed by cross coupling of two NOR

Case 1:When R=S=0

Case 2: When S=0 & R=1

Case 3: When S=1 & R=0

Case 4: When S=1 & R=1

❖ Because the high inputs of S and R, violates the rule of flip

❖ The table below summarizes above explained working of SR

S’R’ LATCH USING NAND GATES

❖ So both the inputs of the NAND gate with S input are 1.

❖ So the flip flop is in undefined state (or forbidden state).

RS/S’R’ Latches as Switch Debouncers

❖ This non – ideal behavior of the switch is called switch bounce

❖ This can result in variation of pulse signals and these series of

❖ We use switch in our day to day life to switch ON/OFF a bulb

❖ This occurs because, when we turn the switch, the

From the timing diagram it is evident that there are several

Department of Electrical & Electronics Engineering

Flip Flops & Applications

❖ Flip-flop is a basic digital memory circuit, which stores one

❖ It is also known as a bistable multivibrator or a binary or

❖Types of positive edge triggered flip – flops (Synchronous

❖From the truth table of SR Flip-Flop, we observe that when

❖It works similar to SR FF. The only difference is that there is no

❖When both J=K=1, the output toggles.

Toggling is changing of output of the flip flop to opposite States

❖Data FF is used in memory chips to store bits of data.

❖Preferably can be used in the design of Shift Registers.

Department of Electrical & Electronics Engineering

Flip Flops & Applications

❖Characteristic equation gives the next state equation of a given

❖To derive the characteristic equation of a FF, write the function

1. SR Flip Flop Characteristic Equation:

CLK S R Qn (present Q n+1 (next

The Next State Equation is Q n+1 = S+R’Q

2. JK Flip-Flop Characteristic Equation:

The Next State Equation is Q n+1 = JQ’+K’Q

3. Data Flip-Flop Characteristic Equation:

K-Map to determine Q n+1

K-Map to determine Q n+1

The Next State Equation is Q n+1 = TQ’+T’Q= T EXOR Q

Department of Electrical & Electronics Engineering

Flip Flops & Applications

Why Application Tables ?

❖ Application Tables will help in designing Synchronous

❖ With the knowledge of basic functioning of F/F, one can write

Application Table of S R F/F:

Function Table of S R F/F is as follows;

Application Table of J K F/F:

Function Table of J K F/F is as follows;

Application Table of D F/F:

Function Table of D F/F is as follows;

Application Table of T F/F:

Function Table of T F/F is as follows;

Department of Electrical & Electronics Engineering