FLIP FLOPS

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Flip-flops
 Computers and calculators use Flip-flop for
their memory. A combination of number of flip
flops will produce some amount of memory.
 Flip flop is formed using logic gates, which are
in turn made of transistors.
 Flip flop are basic building in the
blocks memory of electronic devices.
 Each flip flop can store one bit of data.
 These are also called as sequential
logic circuits.
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Flip-flops
 Flip – flops have two stable states and hence
they are bistable multivibrators.
 The two stable states are High (logic 1) and
Low (logic 0).
 The term flip – flop is used as they can switch
between the states under the influence of a
control signal (clock or enable) i.e. they can
‘flip’ to one state and ‘flop’ back to other state.
 Flip – flops are a binary storage device
because they can store binary data (0 or 1).

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Flip-flops
 Flip – flops are edge sensitive or edge triggered
devices i.e. they are sensitive to the transition rather
than the duration or width of the clock signal.
 They are also known as signal change sensitive
devices which mean that the change in the level of
clock signal will bring change in output of the flip flop.
 Flip flops are also used to control the digital circuit’s
functionality. They can change the operation of a
digital circuit depending on the state.

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Flip-flops
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 Where we use flip flops?
 Registers: As the flip flops have two stable
states, we use them in memory elements like
registers, for data storage. Generally we use
registers in electronic devices like computers.

 Counters: The groups of interconnected flip

flops are uses as counters, to
count the or decrement of an
increment event
occurrence.
Flip-flops
 Where we use flip flops?
 Frequency division: Flip flops are used
as frequencydivision circuits, which divide
the
input frequency exactly to itshalf.
to Frequency circuits are used to
division the frequency of electronic circuits.
regularize

 Data transfer: We use shift registers (A

special-type of registers) to transfer the data
from one flip flop to another, which are
connected in a specific order.
Flip-flops
 SR flip-flop: Besides the CLOCK input, an SR
flip-flop has two inputs, labeled SET and
RESET.

 If the SET input is HIGH when the clock

triggered,
is Q output goes HIGH. If
the RESET is when the the
triggered,input
the Q HIGH
output goes LOW. clock
is
Flip-flops
 SR flip-flop:
 Note that in an SR flip-flop, the SET and
RESET inputs shouldn’t both be HIGH when
the clock is triggered.

 This is considered an invalid input condition,

and the resulting output isn’t predictable if this
condition occurs.
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 SR flip-flop:
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 D flip-flop:
Flip-flops
 D flip-flop:
 D flip flop is actually a slight modification of the
clocked SR flip-flop.
 From the figure you can see that the D input is
connected to the S input and the complement
of the D input is connected to the R input.
 The D input is passed on to the flip flop when
the value of CP is ‘1’. When CP is HIGH, the
flip flop moves to the SET state. If it is ‘0’, the
flip flop switches to the CLEAR state.
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 J-K flip-flop:
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 J-K flip-flop:
 A J-K flip can also be defined as a
flop the S-R flip flop. The only
modificationis that the intermediate state is
difference
of
more refined and precise than that of a S-R
flip flop.
 The behavior of inputs J and K is same as the
S and R inputs of the S-R flip flop. The letter J
stands for SET and the letter K stands for
CLEAR.
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 J-K flip-flop:
 When both the inputs J and K have a HIGH
state, the flip-flop switch to the complement
state. So, for a value of Q = 1, it switches to
Q=0 and for a value of Q = 0, it switches to
Q=1.
 The circuit includes two 3-input AND gates.
The output Q of the flip flop is returned back
as a feedback to the input of the AND along
with other inputs like K and clock pulse [CP].
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 J-K flip-flop:
 So, if the value of CP is ‘1’, the flip flop gets a
CLEAR signal and with the condition that the
value of Q was earlier 1.
 Similarly output Q’ of the flip flop is given as a
feedback to the input of the AND along with
other inputs like J and clock pulse [CP].
 So the output becomes SET when the value of
CP is 1 only if the value of Q’ was earlier 1.
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 J-K flip-flop:
 The output may be repeated in transitions
once they have been complimented for J=K=1
because of the feedback connection in the JK
flip-flop.
 This can be avoided by setting a time duration
lesser than the propagation delay through the
flip-flop. The restriction on the pulse width can
be eliminated with a master-slave or edge-
triggered construction.
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 T flip-flop:
 This is a much simpler version of the J-K flip
flop. Both the J and K inputs are connected
together and thus are also called a single input
J-K flip flop.
 When clock pulse is given to the flip flop, the
output to toggle. Here also the
begins
restriction on the pulse width can
with a master-slave orbe edge-
eliminatedconstruction.
triggered
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 T flip-flop: