Logic Circuits and Design

CPE0021
 Module 7
Sequential Circuits
• "Flip-flop" is the
common name given to
two-state devices which
offer basic memory for
sequential logic
operations.
• Sequential logic circuits
are differentiated from
combinational circuits by
the presence of memory
elements.
• The basic memory elements are the flip-flops or bistable
multivibrators.
• Flip-flops are heavily used for digital data storage and transfer and
are commonly used in banks called "registers" for the storage of
binary numerical data.

Types of Flip-Flops
➢ RS or SR Flip-flop (Set-Reset)
➢ JK Flip-flop
➢ D Flip-flop (Data)
➢ T Flip-flop (Toggle)
Flip-flop Inputs

1. Synchronous Flip-flop Inputs

• The normal data inputs to a flip flop (D, S and R, or J and K) are
referred to as synchronous inputs because they have effect on the
outputs (Q and not-Q) only in step, or in sync, with the clock signal
transitions.

2. Asynchronous Flip-flop Inputs

• These extra inputs are called asynchronous because they can set or
reset the flip-flop regardless of the status of the clock signal. Typically,
they are called preset and clear.
 Synchronous Flip-flop Inputs

RS or SR Flip-flop (Set-Reset)
• To create an S-R latch, we can wire two NOR gates in such a way that
the output of one feeds back to the input of another, and visa-versa, like
this:

* *
• In an S-R latch, activation of the S input sets the circuit, while activation
of the R input resets the circuit.
• If both S and R inputs are activated simultaneously, the circuit will be in
an invalid condition. A race condition (*) is a state in a sequential
system where two mutually-exclusive events are simultaneously
initiated by a single cause.
• In semiconductor form, S-R latches come in prepackaged units. They
are symbolized as:
S Q

R Q
Clocked RS Flip-flop
• An RS flip-flop can be made into
a synchronous device with the
introduction of a clock signal.
• Usually, the clock signal is
called CP, CLK, or CK.
• In semiconductor form, clocked
RS flip-flops come in S Q
prepackaged units . They are
symbolized as:
R Q
RS Flip-flop Timing Diagram

S Q Set Hold Reset Hold

R Q
S

RS Flipflop R

Q
 high
rising or positive edge falling or negative edge

low

S Q CLK

R Q S

Active High
R
RS Flipflop
Q
 S Q CLK

R Q S
Active Low
RS Flipflop R

S Q CLK

R Q S
Positive-edge
R
Triggered
RS Flipflop Q
 S Q CLK

R Q S
Negative-edge
R
Triggered
RS Flipflop Q
 S Q CLK

R Q S
Negative-edge
R
Triggered
RS Flipflop Q
D Flip-flop (Data)
• It is also called Delay flip-flop because that is how it is used. Data is
delayed from output Q by one clock pulse.
• A D latch is like an S-R latch with only one input: the "D" input.
• Activating the D input sets the circuit, and de-activating the D input
resets the circuit. Of course, this is only if the enable input (E) is
activated as well. Otherwise, the output(s) will be latched, unresponsive
to the state of the D input.
• D latches can be used as 1-bit memory circuits, storing either a "high" or
a "low" state when disabled, and reading" new data from the D input
when enabled.
D Flip-flop Timing Diagram
D Q D

Q Q

D Flipflop
Q
 D Q CLK
CLK
Q D
Active High
D Flipflop Q

D Q CLK
CLK
Q D
Active Low
D Flipflop
Q
 D Q CLK
CLK
Q
D
Positive-edge
Triggered Q
D Flipflop

D Q CLK
CLK
Q
D
Negative-edge
Triggered
D Flipflop Q
JK Flip-flop
• The JK flip flop is the most versatile flip-flop, and the most commonly
used flip flop when discrete devices are used to implement arbitrary
state machines.
• Another variation of bistable multivibrators is the J-K flip-flop.
Essentially, this is a modified version of an S-R flip-flop with no "invalid"
or "illegal" output state.
• It is always edge triggered; normally on the falling edge. (some JK flip-
flops; e.g., 74109, trigger on the positive edge.)
• When both J and K inputs are activated, and the clock input is pulsed,
the outputs (Q and not-Q) will swap states. That is, the circuit will toggle
from a set state to a reset state, or visa-versa.
JK Flip-flop
• The JK flip flop is the most versatile flip-flop, and the most commonly
used flip flop when discrete devices are used to implement arbitrary
state machines.
• Another variation of bistable multivibrators is the J-K flip-flop.
Essentially, this is a modified version of an S-R flip-flop with no "invalid"
or "illegal" output state.
• It is always edge triggered; normally on the falling edge. (some JK flip-
flops; e.g., 74109, trigger on the positive edge.)
• When both J and K inputs are activated, and the clock input is pulsed,
the outputs (Q and not-Q) will swap states. That is, the circuit will toggle
from a set state to a reset state, or visa-versa.
Two basic types of JK flip-flops.
1. An RS flip-flop with its outputs and ANDed together with J and K
respectively.
• Note that the connection between the outputs and the inputs to the
AND gates determines the input conditions to R and S when J = K
= 1. This connection is what causes the toggling, and eliminates the
invalid condition which occurs in the RS flip flop.
2. A master-slave flip flop
• This consists of two RS flip flops arranged so that when the
clock pulse enables the first, or master, latch, it disables the
second, or slave, latch. When the clock changes state again
(i.e., on its falling edge) the output of the master latch is
transferred to the slave latch. Again, toggling is accomplished by
the connection of the output with the input AND gates.
 J Q
K Q J

JK Flipflop K

J Q CLK

K Q J

Active High K
JK Flipflop
Q
 J Q CLK

K Q J
Active Low
JK Flipflop K

J Q CLK

K Q J
Positive-edge
K
Triggered
JK Flipflop Q
 J Q CLK

K Q J
Active Low
JK Flipflop K

J Q CLK

K Q J
Positive-edge
K
Triggered
JK Flipflop Q
 J Q CLK

K Q J
Negative-edge
K
Triggered
JK Flipflop Q
T Flip-flop (Toggle)
• The T or "toggle" flip-flop changes its output on each clock edge, giving an
output, which is half the frequency of the signal to the T input.

• Its toggle action is important in the design of constructing binary counters,

frequency dividers, and general binary addition devices.
• It toggles itself with every clock pulse either on the leading edge, or on the
trailing edge.
• T flip-flop is not usually found as an IC chip by itself. However, it can be
constructed using any of the three flip-flops: RS flip-flop, D flip-flop, or JK flip-
flop.
Construction of T flip-flop from a RS flip-flop
• The Q of RS flip-flop is connected to the S
input, while the not Q is connected to the R
input.
Construction of T flip-flop from a
J-K flip-flop
• It can be made from a JK flip-
flop by tying both of its inputs
high.
Construction of T flip-flop from a D
flip-flop
• The not-Q output of a D flip-flop is
connected to the D input of input,
the resulting circuit changes state
Asynchronous Flip-flop Inputs
• Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of
clock input status.
• These input are called the preset (PRE) and clear (CLR). The preset input drives the flip-flop to
a set state while the clear input drives it to a reset state.
• When the preset input is activated, the flip-flop will be set (Q=1, not-Q=0) regardless of any of
the synchronous inputs or the clock. When the clear input is activated, the flip-flop will be
reset (Q=0, not-Q=1), regardless of any of the synchronous inputs or the clock.
• It is possible to drive the outputs of a J-K flip-flop to an invalid condition using the
asynchronous inputs, because all feedback within the multivibrator circuit is overridden.
• Preset and clear inputs find use when multiple flip-flops are ganged together to perform a
function on a multi-bit binary word, and a single line is needed to set or reset them all at
once.
Timing Diagram P

D Q Positive-edge triggered D flip-flop with

CLK active high preset and clear
Q
C
P

CLK

Q
 P

T Q
CLK Negative-edge triggered T flip-flop with
Q active high preset and clear
C

CLK

Q
 P

R Q Positive-edge triggered RS flipflop with active low

preset and clear
S Q

C
P

CLK

Q
 P
Negative-edge triggered JK flipflop with active low
preset and clear
J Q
K Q
P

C C

CLK

Q
Combinational Logic Circuit vs. Sequential Circuit

Combinational Logic Circuit

• It refers to circuits whose output is strictly dependent on the present
value of the inputs. Given the same input, the output will always be the
same. As soon as inputs are changed, the information about the
previous inputs is lost, that is, combinational logic circuits have no
memory.

Present Present
Inputs Output
Sequential Logic Circuit
• It refers to circuits whose outputs depend not only on the present input
value but also the past input value are known as sequential logic
circuits.
• The diagram consists of combinational circuit to which memory elements are connected
to form a feedback path. The memory elements are devices capable of storing binary
information within them.
• The combinational part of the circuit receives two sets of input signals: one is primary
(coming from the circuit environment) and secondary (coming from memory elements).
• The particular combination of secondary input variables at a given time is called the
present state of the circuit. The secondary input variables are also known as the state
variables.
• The block diagram shows that the external outputs in a sequential circuit are a function
not only of external inputs but also of the present state of the memory elements.
• The next state of the memory elements is also a function of external inputs and the
present state. Thus a sequential circuit is specified by a time sequence of inputs,
outputs, and internal states.
Asynchronous vs. Synchronous Sequential Circuit

Asynchronous Sequential Circuit

• The transition from one state to another is initiated by the change in the
primary inputs; there is no external synchronization.
• The memory commonly used in asynchronous sequential circuits are time-
delayed devices, usually implemented by feedback among logic gates.
• Thus, asynchronous sequential circuits may be regarded as combinational
circuits with feedback.
• Because of the feedback among logic gates, asynchronous sequential circuits
may, at times, become unstable due to transient conditions. The instability
problem imposes many difficulties on the designer. Hence, they are not as
commonly used as synchronous systems.
Asynchronous vs. Synchronous Sequential Circuit

Synchronous Sequential Circuit

• Synchronous sequential circuits change their states and output values at

discrete instants of time, which are specified by the rising and falling edge
of a free-running clock signal.
Sequential circuit analysis is useful when:
1. You need to determine the functionality of an existing sequential circuit,
or
2. You want to make changes to an existing sequential circuit, and need to
verify the new behavior
Procedures for analyzing a sequential circuit:
Derive the state equations
(Boolean Expression)

Derive the state excitation table

Derive state transition table

Derive state diagram

Step 1. Derive the state (excitation) equations
1.1 Define the inputs from the circuit.
• These are signals going to the circuit whose source is external.
1.2 Define the outputs from the circuit.
• These are signals generated by the circuit going to other parts of
the circuit or outside of the circuit.
1.3 Define the state variables from the circuit.
• These are the output of the flip-flops.
1.4 Extract the Flip-flop state excitation equations from the circuit.
• These are the inputs to the flip-flops.
Step 2. Derive the state excitation table.
• This table is constructed with the rows indicating all the Present
States and the columns the Present Inputs. Each cell in the table
indicates the flip-flop excitation, i.e. the inputs to the flip-flops.
Step 3: Construct the State Transition Table.
• This table shows the present inputs and the next input states.
Step 4. Construct the State Diagram.
• This diagram is constructed with each state represented by a node
and each input by a transition.
Illustrative Example
Derive the state diagram of the synchronous sequential circuit shown
below.
x
D A

D B

CLK B

Y
Solution:
Step 1. Derive the state equations
Derive 2 equations, one for each flipflop input:
D0 = Ax + Bx D1 = A’ x
We also derive the equation of the output Y = ( A + B ) x’
Step 2. Derive the state excitation table.
Present State Input FF Inputs Present State Output
A B x DA DB A B Y
0 0 0 0 0 0 0 0
0 0 1 0 1 0 1 0
0 1 0 0 0 0 0 1
0 1 1 1 1 1 1 0
1 0 0 0 0 0 0 1
1 0 1 1 0 1 0 0
1 1 0 0 0 0 0 1
1 1 1 1 0 1 0 0
Step 3: Construct the State Transition Table.
Step 4. Construct the State Diagram.
Exercises
Derive the state diagram of the following sequential circuits.

Circuit 1.
Circuit 2.
Circuit 3.
Circuit 4.
Circuit 5.
Circuit 6.
Procedure in designing synchronous sequential circuit
Step 1. Construct the state table.
• The state table is constructed with each state represented by a node and
each input by a transition.
Step 2. Construct the excitation table.
• The excitation table is constructed with the rows indicating all the Present
States, next state, i.e. the outputs of the flip-flops after the clock is asserted.
This step is aided by the use of the Flip-flop Input Table.
Step 3. Derive the simplified Boolean equations.
• Use Karnaugh map to derive the equations for the flipflop inputs and external
output.
Step 4. Draw the logic circuit.
• Draw the circuit diagram from the Flip-flop Excitation Equations and the
Output Equations.
Example 1.
Design a synchronous sequential circuit whose state diagram is shown
below. The type of flip-flop to be use is J-K.
Step 1. Generate the state table.
• Note that there is no output section for this circuit. Two flip-flops are needed
to represent the four states and are designated Q0Q1. The input variable is
labelled x.
Step 2. Derive the excitation table
• The table is now arranged in a different form, where the present
state and input variables are arranged in the form of a truth table.
• The excitable for the JK flip-flop
Step 2. Derive the excitation table
• The table is now arranged in a different form, where the present
state and input variables are arranged in the form of a truth table.
• The excitable for the JK flip-flop
Excitation table of the circuit
➢In the first row of circuit excitation table, we have a transition for flip-flop Q0
from 0 in the present state to 0 in the next state. In JK excitation table, we
find that a transition of states from 0 to 0 requires that input J = 0 and input K
= X. So 0 and X are copied in the first row under J0 and K0 respectively.

➢Since the first row also shows a transition for the flip-flop Q1 from 0 in the
present state to 0 in the next state, 0 and X are copied in the first row under
J1 and K1. This process is continued for each row of the table and for each
flip-flop, with the input conditions as specified in JK excitation table.
Step 3. Derive the simplified Boolean functions.
• The input variables are Q0, Q1, and x; the output are the variables J0,
K0, J1 and K1. The information from the truth table is plotted on the
Karnaugh maps shown.
 • The flip-flop input functions are derived:
J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0¤x
Note: the symbol ¤ is exclusive-NOR.
Step 4. Draw the logic diagram
 • The flip-flop input functions are derived:
J0 = Q1*x' K0 = Q1*x
J1 = x K1 = Q0'*x' + Q0*x = Q0¤x
Note: the symbol ¤ is exclusive-NOR.
Step 4. Draw the logic diagram
Exercise 1.
Design a sequential circuit specified by the table below, using JK flip-
flops.
Exercise 2.
Design a synchronous
sequential circuit whose state
diagram is shown below. Use JK
flip-flops.