LACHS & FLIP FLOP

Latch :
Latch is an electronic device, which changes its output
immediately based on the applied input. It is used to store either 1
or 0 at any specified time. It consists of two inputs namely “SET”
and RESET and two outputs, which are complement to each other.

Flip-Flop :
Flip-flop is a basic digital memory circuit, which stores one bit of
information. Flip flops are the fundamental blocks of most
sequential circuits. It is also known as a bistable multivibrator or
a binary or one-bit memory. Flip-flops are used as memory
elements in sequential circuit.
The output is obtained in a sequential circuit from
combinational circuit or flip-flop or both. The state of flip-flop
changes at active state of clock pulses and remains unaffected
when the clock pulse is not active.
SR Latch
The SR latch is
- a circuit with two cross-coupled NOR gates or two cross-coupled
NAND gates
- Two inputs labeled S for set and R for reset.
The SR latch has two useful states When output Q = 1 and Q’ = 0, the
latch is said to be in the set state . When Q = 0 and Q’ = 1, it is in the
reset state . Outputs Q and Q’ are normally the complement of each
other.
D Latch (Transparent Latch) One way to eliminate the undesirable
condition of the indeterminate state in the SR latch is to ensure that
inputs S and R are never equal to 1 at the same time. This is done in
the D latch . This latch has only two inputs: D (data) and En (enable).
The D input goes directly to the S input, and its complement is applied
to the R input. As long as the enable input is at 0, the cross-coupled SR
latch has both inputs at the 1 level and the circuit cannot change state
regardless of the value of D . The D input is sampled when En = 1. If D
= 1, the Q output goes to 1, placing the circuit in the set state. If D = 0,
output Q goes to 0, placing the circuit in the reset state.
What is the D Flip Flop used for?
The D Flip Flop acts as an electronic memory component since the
output remains constant unless deliberately changed by altering the
state of the D input followed by a rising clock signal.
Where are D Flip Flops used?
The D Flip Flop is a building block shift registers. For example, by
cascading eight D Flip Flops in sequence, a byte (8-bits) of
information can be stored after 8 clock cycles.
What else can they be used for?
By connecting the inverting output of the D Flip Flop to the D input, a
simple divide by two circuit is created i.e. the D output changes state
at half the frequency of the clock signal. By cascading D flip flops and
through appropriate design of external combinational logic gates, a
countdown timer can be created.
Types of flip-flops:
1- RS Flip Flop
2- D Flip Flop
3-JK Flip Flop
4- T Flip Flop
TYPE OF FLIP FLOP

1- D FLIP FLOP

Definition
A D (or Delay) Flip Flop is a digital electronic circuit used
to delay the change of state of its output signal (Q) until the next
rising edge of a clock timing input signal occurs.
3- JK FLIP FLOP
- The JK flip flop was termed after his inventor jack Kilby
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it
has the following switching problems:
- When Set 'S' and Reset 'R' inputs are set to 0, this condition
is always avoided.
- When the Set or Reset input changes their state while the
enable input is 1, the incorrect latching action occurs.
The JK Flip Flop removes these two drawbacks of SR Flip
Flop.
The JK flip flop is one of the most used flip flops in digital
circuits. The JK flip flop is a universal flip flop having two inputs 'J'
and 'K'. In SR flip flop, the 'S' and 'R' are the shortened
abbreviated letters for Set and Reset, but J and K are not. The J
and K are themselves autonomous letters which are chosen to
distinguish the flip flop design from other types.
The JK flip flop work in the same way as the SR flip flop work. The
JK flip flop has 'J' and 'K' flip flop instead of 'S' and 'R'. The only
difference between JK flip flop and SR flip flop is that when both
inputs of SR flip flop is set to 1, the circuit produces the invalid
states as outputs, but in case of JK flip flop, there are no invalid
states even if both 'J' and 'K' flip flops are set to 1.

The JK Flip Flop is a gated SR flip-flop having the addition of a

clock input circuitry. The invalid or illegal output condition occurs
when both of the inputs are set to 1 and are prevented by the
addition of a clock input circuit. So, the JK flip-flop has four
possible input combinations, i.e., 1, 0, "no change" and "toggle".
The symbol of JK flip flop is the same as SR Bistable Latch except
for the addition of a clock input.
Registers and Counters
in Digital Logic
flip-flop is a 1 bit memory cell which can be used for storing the digital data. To increase
the storage capacity in terms of number of bits, we have to use a group of flip-flop. Such a
group of flip-flop is known as a Register. The n-bit register will consist of n number of flip-
flop and it is capable of storing an n-bit word.
The binary data in a register can be moved within the register from one flip-flop to
another. The registers that allow such data transfers are called as shift registers. There are
four mode of operations of a shift register.
- Serial Input Serial Output
- Serial Input Parallel Output
- Parallel Input Serial Output
- Parallel Input Parallel Output

Rotate and Shift operations

Counters
Design a 3-bit Counter using T Flip flop
https://www.youtube.com/watch?v=hJIST1cEf
6A
State Diagram
https://www.javatpoint.com/jk-flip-flop-in-digital-electronics

https://www.youtube.com/watch?v=b-eAGeMakEM