Analog and Digital VLSI Design

(EEE/ INSTR F313)

BITS Pilani
Pilani Campus
Instructor : Dr. KAVINDRA KANDPAL
Note to students
• The slides are introductory and doesn’t include all the syllabus.
• For understanding linear delay model using logical effort, please read the
following article:
Sproull, R. F., & Sutherland, I. E. (1991). Logical effort: Designing for speed on the back
of an envelope. IEEE Advanced Research in VLSI, 1-16.

Following are the other references followed for this particular section:
• Chapter 6: Designing Combinational logic gates in CMOS from J.M. Rabaey.
• CMOS VLSI Design A circuit and systems perspective by Neil H.E. Weste and
David M. Harris, 4th edition, Linear delay model Section 4.4, Section 4.5.
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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model
 First proposed by Ivan Sutherland and Bob Sproull in 1991. Sproull, R. F., & Sutherland, I. E.
(1991). Logical effort: Designing for speed on the back of an envelope. IEEE Advanced Research in
VLSI, 1-16.

 Delay of a logic gate is composed of two components: d = f + p

where f is effort delay and p is parasitic delay and unit is τ which is technology specific.

 Effort delay f itself has two components and can be defined as: f=gh
where g is known as logical effort, and h is known as electrical effort = Cout/ Cin (the
ratio of output capacitance to input capacitance)

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Method of logical effort BITS Pilani, Pilani Campus
Logical effort

 Complexity of logic function (Invert, NAND,

NOR, etc)
 Standard inverter has logical effort = 1
 Logical effort of any other logic function describe
how much worse it is than an inverter at
producing output current, given an equivalent
amount of input capacitance
 More complex gates have greater logical efforts,
indicating that they take longer to drive a given
fanout.
 Depends only on topology not transistor sizing.
Resource: CMOS VLSI Design A circuit and systems perspective 4
Method of logical effort BITS Pilani, Pilani Campus
Logical effort

 Logical effort of any other logic function describe how much worse it is than an
inverter at producing output current, given an equivalent amount of input
capacitance.

Logical effort of a gate is defined as the ratio of the input capacitance of the gate
to the input capacitance of an inverter that can deliver the same output current.
Resource: CMOS VLSI Design A circuit and systems perspective 5
Method of logical effort BITS Pilani, Pilani Campus
Logical effort calculation

Transistors are sized as unit resistor. i.e. by considering the mobility of nMOS and pMOS
Resource: CMOS VLSI Design A circuit and systems perspective 6
Method of logical effort BITS Pilani, Pilani Campus
Logical effort calculation

Gate type Number of inputs

1 2 3 4 n
Inverter 1
NAND 4/3 5/3 6/3 (n+2)/3
NOR 5/3 7/3 9/3 (2n+1)/3
Tristate / mux 2 2 2 2 2
XOR, XNOR 4, 4 6, 12, 6 8, 16, 16, 8
Resource: CMOS VLSI Design A circuit and systems perspective 7
Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model

 The logical effort of a logic function depends mainly on the circuit topology and
slightly on the electrical properties of the fabrication process used to build it.
 Logical effort of individual stages of logic can be combined to find the logical
effort of networks.

 The Electrical effort h describes how the electrical environment of the logic gate
affects performance and how the size of the transistors in the gate determines its
load driving capability.

Resource: CMOS VLSI Design A circuit and systems perspective 8

Method of logical effort BITS Pilani, Pilani Campus
 For SOI Technology, Parasitic delay is
Linear Delay Model less

 The parasitic delay (p) of a gate is the delay of the gate when it drives zero load.
It can be estimated with RC delay models.

 Parasitic delay of an inverter (pinv) is the ratio of diffusion capacitance to gate

capacitance in a particular process and it is usually close to 1.

 The 3-input NAND and NOR each have 9 units of diffusion capacitance on the
output, so the parasitic delay is three times as great (3*pinv).

 Parasitic delay of n-input NOR and NAND is n*pinv

 Increasing transistor sizes reduces resistance but increases capacitance
correspondingly, so parasitic delay is, on first order, independent of gate size. 9
Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model

Sproull, R. F., & Sutherland, I. E. (1991). Logical effort: Designing for speed on the back of an envelope. IEEE
Advanced Research in VLSI, 1-16. 10
Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model

Estimate the delay of a fanout-of-4 (FO4) inverter

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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model

• Path Logical Effort G   gi

Cout-path
• Path Electrical Effort H
Cin-path
In the paths that includes branch, F = ?

• Path Effort F   f i   gi hi

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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model

Cout-path
• Path Electrical Effort H
Cin-path

Con path  Coff path

• Branching Effort b
Con path
B   bi F=GBH
Resource: CMOS VLSI Design A circuit and systems perspective 13
Method of logical effort BITS Pilani, Pilani Campus
Multistage Delays

• Path Effort Delay DF   f i

• Path Parasitic Delay P   pi

• Path Delay D   d i  DF  P

Resource: CMOS VLSI Design A circuit and systems perspective 14

Method of logical effort BITS Pilani, Pilani Campus
Optimizing for the delay of a given path
(without optimizing number of stages)

D   d i  DF  P

• Delay is smallest when each stage bears same effort

ˆf  g h  F N1
i i

1
• Thus minimum delay of N stage path is D  NF  P
N

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Method of logical effort BITS Pilani, Pilani Campus
Optimizing for the delay of a given path
(without optimizing number of stages)

• How to Size a transistor in a logic path ?

ˆf  gh  g Cout
Cin

gi Couti
 Cini 
fˆ

• Working backward, apply capacitance transformation to find input

capacitance of each gate given load it drives.
• Verify by if input cap spec is met.
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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model: Examples
Estimate the minimum delay of the path from A to B and choose
transistor sizes to achieve this delay

y
x
45
A 8
x
y B
45

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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model: Examples

y
x
45
A 8
x
y B
45

F = GBH = 125
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4
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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model: Examples

F = GBH = 125
Parasitic Delay P = 2 + 3 + 2 = 7
Delay D = 3*5 + 7 = 22 = 4.4 FO4

45
y = 45 * (5/3) / 5 = 15
A P: 4
x = (15*2) * (5/3) / 5 = 10 P: 4
N: 4 P: 12 B
N: 6 45
N: 3

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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model: Example (Take home)

The critical path of a logic circuit is

shown in Fig. (Node A to node B).
Optimize the path for minimum
delay using the method of logical
effort. Calculate the Width (W) of
each transistor on the critical path,
assuming all transistors have 𝐿 =
𝐿𝑚𝑖𝑛 = 250 𝑛𝑚.
Given: capacitance at node A is 4
fF, capacitance at node B is 100 fF,
𝐶𝑜𝑥 = 2.5 fF/µm2, μnCox = 120
μA/V2, μpCox = 40 μA/V2 .
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Method of logical effort BITS Pilani, Pilani Campus
Linear Delay Model: Example-2
A control unit generates a signal from a unit-
sized inverter. The signal must drive unit-sized
loads in each bitslice of a 64-bit datapath. The
designer can add inverters to buffer the signal
to drive the large capacitive load. Assuming
polarity of the signal does not matter, what is
the best number of inverters to add and what
delay can be achieved?

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Methodperspective
Resource: CMOS VLSI Design A circuit and systems of logical effort BITS Pilani, Pilani Campus
Optimal Number of stages

Let’s define a term ρ as:

Method of logical effort 22 BITS Pilani, Pilani Campus
Optimal Number of stages

Solution of this equation will give optimal number of stages. However,

it doesn’t have any closed form solution.

Solving numerically, when pinv = 1, we find ρ = 3.59.

Resource: CMOS VLSI Design A circuit and systems perspective

Method of logical effort 23 BITS Pilani, Pilani Campus
Optimal Number of stages

2.4 < ρ < 6 gives delay within 15% of

optimal.

For simplicity take ρ = 4

Method of logical effort 24 BITS Pilani, Pilani Campus

Optimal Number of stages: Summary
 Compute path effort F  GBH
 Estimate best number of stages 𝑁 = 𝑙𝑜𝑔 𝐹
4
 Sketch path with 𝑁 stages
1
 Estimate least delay D  NF  PN

 Determine best stage effort ˆf  F N1

gi Couti
 Find gate sizes Cini 
fˆ
Resource: CMOS VLSI Design A circuit and systems perspective
Method of logical effort 25 BITS Pilani, Pilani Campus