Delay in

Multistage
Logic
Networks
Ref: Weste-Harris

1
Delay in Multistage Logic Networks

 Gate Delay: d=f + p=gh + p (what about Path Delay?)

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

CMOS VLSI Design 4th Ed. 2

Delay in Multistage Logic Networks

 Gate Delay: d=f + p=gh + p (what about Path Delay?)

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

 Path Logical Effort G   gi

CMOS VLSI Design 4th Ed. 3

Delay in Multistage Logic Networks

 Gate Delay: d=f + p=gh + p (what about Path Delay?)

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

 Path Logical Effort G   gi

Cout-path
 Path Electrical Effort H
Cin-path


CMOS VLSI Design 4th Ed. 4

Delay in Multistage Logic Networks

 Gate Delay: d=f + p=gh + p (what about Path Delay?)

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

 Path Logical Effort G   gi

Cout-path
 Path Electrical Effort H
Cin-path
 Path Effort F   f i   gi hi
CMOS VLSI Design 4th Ed. 5
 Delay in Multistage Logic Networks

 Introduce branching effort

– Accounts for branching between stages in path

– branching effort b

– path branching effort B   bi

 Path Effort with branching F = GBH

6: Logical Effort CMOS VLSI Design 4th Ed. 7

 Delay in Multistage Logic Networks

10
x z
y
20
g1 = 1 g2 = 5/3 g3 = 4/3 g4 = 1
h1 = x/10 h2 = y/x h3 = z/y h4 = 20/z

 Path Effort Delay DF   f i

 Path Parasitic Delay P   pi

 Path Delay D   d i  DF  P
6: Logical Effort CMOS VLSI Design 4th Ed. 9
 Designing Fast Circuits
 Path Delay D   d i  DF  P
 Delay is smallest when each stage bears same effort. If a
path has N stages and each bears the same effort, that
effort must be ˆ 1
f  gi hi  F
N

 Thus minimum delay of N stage path is

1
D  NF  PN

 This is a key result of logical effort

– Find fastest possible delay
– Doesn’t require calculating gate sizes
CMOS VLSI Design 4th Ed. 10
 Example: 3-stage path
 Estimate the minimum delay of the path from A to B
and choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

6: Logical Effort CMOS VLSI Design 4th Ed. 12

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

2-input NAND

6: Logical Effort CMOS VLSI Design 4th Ed. 13

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

3-input NAND

6: Logical Effort CMOS VLSI Design 4th Ed. 14

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

2-input NOR

6: Logical Effort CMOS VLSI Design 4th Ed. 15

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

p = 6RC
p(normalized)
2-input NAND = 6RC/ 3RC =2

6: Logical Effort CMOS VLSI Design 4th Ed. 16

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

x 2 2 2
x
y
3 9C
45
5C
A 8
x 3 3C
y B
45
5C
3 3C
5C

p = 9RC
p(normalized)
3-input NAND = 9RC/ 3RC =3

6: Logical Effort CMOS VLSI Design 4th Ed. 17

 Example: 3-stage path
 Estimate the minimum delay of the path from A to B and
choose transistor sizes to achieve this delay.

y
x
45
A 8
x
y B
45

p = 6RC
p(normalized)
2-input NOR = 6RC/ 3RC =2

6: Logical Effort CMOS VLSI Design 4th Ed. 18

 Example: 3-stage path
x

y
x
45
A 8
No of stages N = 3
x
y B
45

Logical Effort G = (4/3)*(5/3)*(5/3) = 100/27

Electrical Effort H = 45/8
Branching Effort B=3*2=6
Path Effort F = GBH = 125
Best Stage Effort fˆ  3 F  5
Parasitic Delay P=2+3+2=7
Delay D = 3*5 + 7 = 22

6: Logical Effort CMOS VLSI Design 4th Ed. 21

 Example: Sizes in 3-stage path
For least delay, f1 = f2 = f3 = 5
g1=4/3
g2=5/3
g3=5/3
x
h1=(3*x)/8
y
x
45 h2=(2*y)/x
A 8 h3=45/y
x
y B
45

we can calculate values of x and y

from the following equations
f1 = g1h1
f2 = g2h2
f3 = g3h3

6: Logical Effort CMOS VLSI Design 4th Ed. 22

 Example: Sizes in 3-stage path

y
x
45
A 8
x
y B
45
y = 15
x = 10

45
A P: 4
P: 4
N: 4 P: 12 B
N: 6 45
N: 3

6: Logical Effort CMOS VLSI Design 4th Ed. 25

 Choosing the Best Number of Stages

 How many stages should a path use?

– Minimizing number of stages is not always fastest
– Gate delay depends on the electrical effort, so
sometimes using fewer stages results in more
delay

6: Logical Effort CMOS VLSI Design 4th Ed. 26

 Example: Choosing the Best Number
of Stages
 Example: A control unit generates a signal from a
unit-sized inverter. The signal must drive unit-sized
loads in each bitslice of a 64-bit datapath. The
designer can add inverters to buffer the signal to
drive the large load. Assuming polarity of the signal
does not matter, what is the best number of inverters
to add and what delay can be achieved?

6: Logical Effort CMOS VLSI Design 4th Ed. 27

 Example: Choosing the Best Number
of Stages
 Example: drive 64-bit datapath with unit inverter
 Figure shows the cases of adding 0, 1, 2, or 3
inverters (N = 1, 2, 3, 4).
 The path electrical effort is H = 64.
 The path logical effort is G = 1,
independent of the number of
inverters
 Thus, the path effort is F = 64.
 The inverter sizes are chosen
to achieve equal stage effort.

6: Logical Effort CMOS VLSI Design 4th Ed. 28

 Best Number of Stages
 Example: drive 64-bit datapath with unit inverter
 Figure shows the cases of adding 0, 1, 2, or 3
inverters (N = 1, 2, 3, 4).
Initial Driver 1 1 1 1

8 4 2.8

D = NF1/N + P
16 8

= N(64)1/N + N [here, P=N]

23

Datapath Load 64 64 64 64

N: 1 2 3 4
f: 64 8 4 2.8
D: 65 18 15 15.3
Fastest

6: Logical Effort CMOS VLSI Design 4th Ed. 29