Arithmetic

Circuits
Ref: Weste-Harris,
Rabaey, Pucknell, M. J.
Flynn

1
 Outline
 Single-bit Addition
 Carry-Propagate Adder
 Carry-Ripple Adder/Ripple-Carry Adder
 Carry-Select Adder
 Carry-Skip Adder
 Carry-Lookahead Adder
 Tree Adder

2
 Single-Bit Addition (HA)
 The circuit which implements the addition of only two bits, is called a
half-adder (HA).

A B

Cout

3
 Single-Bit Addition (FA)
 The circuit which implements the addition of two data bits and a carry-
in bit, is called a full-adder (FA).

A B

Cout C

4
 Single-Bit Addition (HA and FA)
A B A B
Half Adder Full Adder
Cout Cout C

S S

A B Cout S A B C Cout S
0 0 0 0 0 0 0 0 0
0 1 0 1 0 0 1 0 1
1 0 0 1 0 1 0 0 1
1 1 1 0 0 1 1 1 0
1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 1 1

5
 Single-Bit Addition (FA PGK)
 For a full adder, define what happens to carries
(in terms of A and B)
– Generate: Cout = 1 independent of Cin
• G=A•B
– Propagate: Cout = Cin
• P=AB
– Kill: Cout = 0 independent of Cin
• K = ~A • ~B

7
 Half Adder Design

A B

Cout

8
 Full Adder Design I

 The addition function is symmetric; i.e., the function of

complemented inputs is the complement of the function.

9
 Full Adder Design I

A A B B C C

A A

B B
A
B S B
C C C
A B B
S
A
MAJ

Cout C C C A
B Cout
C B
B B C A
A B B
A A

The full adder of the figure employs 32 transistors (6 for the inverters, 10 for the
majority gate, and 16 for the 3-input XOR).
10
 Full Adder Design II
 Factor S in terms of Cout

MINORITY
A
B
C
Cout S
S

Cout

The full adder of the figure employs 28(10+12+6) transistors.

11
 Full Adder Design (Dual-rail domino)

 Dual-rail domino
– Very fast, but large and power hungry
– Used in very fast multipliers
 
Cout _h Cout _l
C_h A_h C_l A_l
A_h B_h B_h A_l B_l B_l

S_l  S_h
C_l
C_h C_h

B_l
B_h B_h

A_h A_l

14
Carry Propagate Addition (N-bit adder)

 N-bit adder (called CPA)

– It takes N-bit inputs {A , …, A }, {B , …, B }, and carry-in Cin,
N 1 N 1

and compute the sum {S , …, S } and the carry-out of the

N 1

most significant bit Cout

AN...1 BN...1

Cout Cin
+

SN...1

15
 Carry Propagate Addition
(Example: 4-bit Addition)
– Each sum bit depends on all previous carries

Cout Cin Cout Cin

00000 11111 carries
1111 1111 A4...1
+0000 +0000 B4...1
1111 0000 S4...1

– Figure 1 shows the addition 11112 + 00002 + 0 (all sum bits 1, all carry bits 0)
– Figure 2 shows the addition 11112 + 00002 + 1 (all sum bits 0, all carry bits 1)

16
 Carry-Ripple Adder
(or Ripple-Carry Adder)
 Simplest design: An N-bit adder is constructed by cascading N
full adders
– Critical path goes from Cin to Cout
– The delay of the adder is set by the time for the carries to
ripple through the N stages
– Design full adder to have fast carry delay

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1
S4 S3 S2 S1

17
 Inversion Property
(Addition is Symmetric)

A B A B

Ci FA Co Ci FA Co

S S

S  A B C i  = S  A B  Ci 

C o  A B C i  = Co  A B  Ci 
 The addition function is symmetric; i.e., the function of complemented
inputs is the complement of the function.

18
 Carry-Ripple Adder
(Minimize Critical Path Delay by Reducing No of Inverters)

Even Cell Odd Cell

A1 B1 A3 B3
A0 B0 A2 B2

Ci,0 C o,0 Co,1 C o,2 C o,3

FA’ FA’ FA’ FA’

S0 S2
S1 S3

Exploit Inversion Property

Note: need 2 different types of cells

19
 Carry-Ripple Adder
(Minimize Critical Path Delay by Reducing No of Inverters)

 Critical path passes through majority gate

– Built from minority + inverter
– Eliminate inverter and use inverting full adder

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1

S4 S3 S2 S1

20
 Carry Select Adder

The adder is divided into blocks. Each block is composed of two adders,
one with a logical 0 carry in and the other with a logical 1 carry in.

The sum and carry out generated are then selected (via MUX) by the
actual carry in which comes from the carry out output of the previous block.
21
 Carry Select Adder

Delay of an n-bit ripple carry adder:

k1: delay through one adder cell

A4 B4 A3 B3 A2 B2 A1 B1

Cout Cin
C3 C2 C1
S4 S3 S2 S1

22
 Carry Select Adder

Delay of an n-bit Carry Select Adder:

The overall delay is composed of two parts:

• the propagation delay through the first block
• the propagation delay through the multiplexers

23
 Carry Select Adder

Delay of an n-bit Carry Select Adder:

No of blocks/groups in the n-bit adder: M
No of adder per block: P = n/M
Total delay:
k1: adder delay
k2: mux delay
For optimization, dT/dM=0, So

24
Carry Skip Adder

26
 Carry Skip Adder

 Figure shows the schematic structure of a 24-bit carry skip adder,

subdivided into four blocks (each 6 bit).
 Carry skip adders take advantage of the group/block propagation
signal (ΠPi).

27
 Carry Skip Adder

 If the block propagation signal = 1, then the carry signal entering the
block can bypass it and be transmitted through a multiplexer to the
next block.

28
 Carry Skip Adder

 If the block propagation signal = 1, then the carry signal entering the
block can bypass it and be transmitted through a multiplexer to the
next block.

29
Carry Skip Adder: Example

30
Carry Skip Adder: Example

No of blocks/groups in the n-bit adder: M

No of adder per block: P = n/M
Total delay:
k1: adder delay
k2: mux delay
For optimization, dT/dM=0, So

31
 Carry Look Ahead Adder

Cin
C0 = A0B0 + Cin(A0 + B0)
= G0 + P0Cin
C1 = A1B1 + C0(A1 + B1)
= G1 + P1C0
= G1 + P1(G0 + P0Cin)
= G1 + P1 G0 + P1P0Cin
C2 = A2B2 + C1(A2 + B2)
= G2 + P2C1
= G2 + P2(G1 + P1 G0 + P1P0Cin)
= G2 + P2 G1 + P2P1G0 + P2P1P0Cin
C3 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0Cin

37
Carry Look Ahead Adder

38
 Carry Look Ahead Adder
(4-bit Adder)
VDD

G3

G2

G1

G0 C3 = G3 + P3G2 + P3P2G1
+ P3P2P1G0 + P3P2P1P0Cin
Ci,0
Co,3

P0

P1

P2

P3

39
 Carry Look Ahead Adder
(4-bit Adder, Multiple Output Domino Logic)

= G3 + P3G2 + P3P2G1 + P3P2P1G0

+ P3P2P1P0Cin
= G2 + P2 G1 + P2P1G0 + P2P1P0Cin

40
Partial Carry Look Ahead Adder
(9-bit Adder)

41
Carry Look Ahead Adder
(4-bit CLA Unit)

42
 Carry Look Ahead Adder
(16-bit Adder with 4-bit CLA Units)

43
 Single-Bit Addition Revisited
(Generate / Propagate)
 For a full adder, define what happens to carries
(in terms of A and B)
– Generate:
• G=A•B
– Propagate:
• P=AB

45
 Carry-Ripple Adder Revisited
(Group Generate / Group Propagate)
 Group generate / group propagate notations are commonly
used in describing faster adders.

 Group generate / group propagate signals describe

whether a group spanning bits i…j, inclusive, generate a
carry or propagate a carry.

46
 Carry-Ripple Adder Revisited
(Group Generate / Group Propagate)
 Equations often factored into G and P
 Generate and propagate for groups spanning i:j

0 GCP
0:00:0 in

 Base case
G0:0  G0  Cin
P0:0  P0  0
 Sum:
Si  Pi  Gi 1:0

48
 Carry-Ripple Adder Revisited
(4-bit Carry-ripple Adder, Bitwise PG Logic)

A4 B4 A3 B3 A2 B2 A1 B1 Cin

1: Bitwise PG logic
G0:0  G0  Cin
G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
P0:0  P0  0

2: Group PG logic

G3:0 G2:0 G1:0 G0:0

C3 C2 C1 C0
3: Sum logic Si  Pi  Gi 1:0

C4

Cout S4 S3 S2 S1

52
 Carry-Ripple Adder Revisited
(4-bit Carry-ripple Adder, Group PG Logic)

A4 B4 A3 B3 A2 B2 A1 B1 Cin

G0:0  G0  Cin
G4 P4 G3 P3 G2 P2 G1 P1 G0 P0
P0:0  P0  0

G3:0 G2:0 G1:0 G0:0

C3 C2 C1 C0

Si  Pi  Gi 1:0
C4

Cout S4 S3 S2 S1

53
 Carry-Ripple PG Diagram
Bit Position

The carry-ripple adder critical 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

path delay is
tripple  t pg  ( N  1)t AO  txor

tpg is the delay of the 1-bit

propagate/generate gates
tAO is the delay of the ANDOR gate

Delay
txor is the delay of the final sum XOR

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

54
Logarithmic Adder
(Tree Adder)

58
Logarithmic Adder
(Tree Adder)

59
Logarithmic Adder
(Tree Adder)

60
 Kogge-Stone Adder

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

15:14 14:13 13:12 12:11 11:10 10:9 9:8 8:7 7:6 6:5 5:4 4:3 3:2 2:1 1:0

15:12 14:11 13:10 12:9 11:8 10:7 9:6 8:5 7:4 6:3 5:2 4:1 3:0 2:0

15:8 14:7 13:6 12:5 11:4 10:3 9:2 8:1 7:0 6:0 5:0 4:0

15:0 14:0 13:0 12:0 11:0 10:0 9:0 8:0 7:0 6:0 5:0 4:0 3:0 2:0 1:0 0:0

62
Kogge-Stone Adder
4-bit Kogge-Stone Adder Example

65
 Multiplication: Example 1
 Example: 1100 : 1210 multiplicand
0101 : 510 multiplier
1100
0000 partial
1100 products
0000
00111100 : 6010 product
 M x N-bit multiplication
– Produce N partial products of M bits each
– Sum these to produce M+N-bit product P

72
 Multiplication: General Form
 Multiplicand: Y = (yM-1, yM-2, …, y1, y0)
 Multiplier: X = (xN-1, xN-2, …, x1, x0)

 M 1   N 1
 N 1 M 1
 Product: P    y j 2 j    xi 2i    xi y j 2i  j
 j 0   i 0  i 0 j 0
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product

73
Binary Multiplication: Example 2

Generating partial products consists of the logical ANDing of the

appropriate bits of the multiplier and multiplicand. Each column of partial
products must then be added.
74
 Dot Diagram
y5 y4 y3 y2 y1 y0 multiplicand
x5 x4 x3 x2 x1 x0 multiplier
x0y5 x0y4 x0y3 x0y2 x0y1 x0y0
x1y5 x1y4 x1y3 x1y2 x1y1 x1y0
x2y5 x2y4 x2y3 x2y2 x2y1 x2y0 partial
x3y5 x3y4 x3y3 x3y2 x3y1 x3y0 products
x4y5 x4y4 x4y3 x4y2 x4y1 x4y0
x5y5 x5y4 x5y3 x5y2 x5y1 x5y0
p11 p10 p9 p8 p7 p6 p5 p4 p3 p2 p1 p0 product
x0

partial products

multiplier x
x15

 Large multiplications are conveniently illustrated using dot diagrams.

 The figure shows a dot diagram for a simple 16 × 16 multiplier.
75
 Array Multiplier
y3 y2 y1 y0

x0

x1
CSA
Array

x2

x3

CPA

p7 p6 p5 p4 p3 p2 p1 p0

A B
Sin A Cin critical path A B
A B
B Sin
= Cout Cin = Cout Cin
Cout Cin
Sout
Cout Sout Sout
Sout

76
 Rectangular Array Multiplier
 Figure shows the same multiplier squashed to fit a rectangular block.
y3 y2 y1 y0

x0

p0
x1

p1
x2

p2
x3

p3

p7 p6 p5 p4

78
Array Multiplier (with AND, HA, FA)
X3 X2 X1 X0
 Array Multiplier with X3 X2 Y0
X1 X0
AND gates, HA (half adder)
and FA (full adder) units Z0
X3 X2 X1 X0 Y1

HA FA FA HA

X3 X2 X1 X0 Y2 Z1

FA FA FA HA

X3 X2 X1 X0 Y3 Z2

FA FA FA HA

Z7 Z6 Z5 Z4 Z3
79
Array Multiplier (with AND, HA, FA)

HA FA FA HA

FA FA FA HA Critical Path 1
Critical Path 2
Critical Path 1 & 2

FA FA FA HA

81
Carry-Save Multiplier

HA HA HA HA

HA FA FA FA

HA FA FA FA

HA FA FA HA

Vector Merging Adder

82
 (3,2) Counter (CSA32)

 A CSA is effectively a “ones counter” that adds the number of 1’s on

the A, B, and C inputs and encodes them on the sum and carry outputs.
 It is therefore also known as a (3,2) counter because it converts three
inputs into a count encoded in two outputs.
A B C Carry Sum No of
1’s
0 0 0 0 0 0
0 0 1 0 1 1
0 1 0 0 1 1
0 1 1 1 0 2
1 0 0 0 1 1
1 0 1 1 0 2
1 1 0 1 0 2
1 1 1 1 1 3
85
Wallace Tree Multiplication

86
 Booth Encoding
 Array multiplier requires N partial products
 Booth Encoding may reduce the number of partial
products which in turn reduces the hardware and
delay required to sum the partial products.

90
 Booth Encoding
 Apply encoding to the multiplier bits before the bits
are used for getting partial products.

91
Booth Encoding

92
Booth Encoding: Example

95
Modified Booth Algorithm

Multiplicand: Y
Multiplier: X

100
Modified Booth Algorithm

105
Modified Booth Algorithm

106
Modified Booth Algorithm

107
Modified Booth Algorithm : Example

109
 Modified Booth Algorithm
(Hardware: Booth Selects)

111
 Modified Booth Algorithm
(Hardware: Booth Selects)

112
 Modified Booth Algorithm
(Hardware : Booth Encoder)

113
 Modified Booth Algorithm
(Hardware : Booth Selector)

114