Sequential

Circuit
Design
Ref: Weste-Harris

1
Sequential and Combinational Circuits

 For combinational circuits, the output is a function of

the current inputs.

 For sequential circuits, the output depends on

previous as well as current inputs; such circuits are
said to have state.

2
 Static and Dynamic Circuits

 Static circuits refer to gates that have no clock input,

such as complementary CMOS, pseudo-nMOS, or
pass transistor logic.

 Dynamic circuits refer to gates that have a clock

input, especially domino logic.

 Sequential circuits can be both static and dynamic.

5
 Static and Dynamic
Sequential Elements
 Sequencing elements themselves can be either
static or dynamic.

 A sequencing element with static storage employs

some sort of feedback to retain its output value
indefinitely.

 An element with dynamic storage generally

maintains its value as charge on a capacitor that will
leak away if not refreshed for a long period of time.

6
 Latches and Flip-flops

 Latches and flip-flops are the two most commonly

used sequencing elements.

 Both latches and flip-flops have three terminals: data

input (D), clock (clk), and data output (Q).

7
 Latches and Flip-flops

 For the latch, when the clock is high, D flows through to

Q as if the latch were just a buffer, but when the clock is
low, the latch holds its present Q output even if D
changes.

 The flip-flop is an edge-triggered device that copies D to

Q on the rising edge of the clock and ignores D at all
other times. 8
Latches and Flip-flops

10
Circuit Design of Latches and Flip-Flops

11
 Latch Design (1)
 Pass Transistor Latch

 Pros
+ Tiny
D Q
+ Low clock load
Used in 1970’s

11: Sequential Circuits 13

 Latch Design (1)
 Pass Transistor Latch 

 Cons D Q
– Output does not swing from rail-to-rail
(gnd to VDD)
– Output never rises above VDD – Vt
– Output is dynamic (if output floats long enough
when the latch is opaque, it can be disturbed by
leakage)
– D drives diffusion input of a pass transistor
(potential noise issues)
– Noise on the output can corrupt the state
11: Sequential Circuits 15
 Latch Design (2)
 Transmission gate

+ No Vt drop
- Requires inverted clock D Q

11: Sequential Circuits 18

 Latch Design (3,4)
 Inverting latch

+ Figure 1 adds an output inverter
X
so that the state node X is isolated D Q

from noise on the output. 


+ Figure 2 also behaves as an
inverting latch with a buffered input D Q
but unbuffered output. 
+ Fixes either
• Output noise sensitivity
• Or diffusion input noise sensitivity
– Inverted output

11: Sequential Circuits 19

 Latch Design (5)
 Buffered input

+ Fixes diffusion input X
D Q
+ Noninverting



 Practical latches need to be staticized, adding

feedback to prevent the output from floating. Static
latches are now essential because of leakage.
 It adds an input inverter so the input is a transistor
gate rather than unbuffered diffusion.
11: Sequential Circuits 22
 Latch Design (6)
 Figure shows a robust  Q
latch that addresses the X
D
deficiencies mentioned so far.



 The latch is static, all nodes swing rail-to-rail, the state

noise is isolated from output noise, and the input drives
transistor gates rather than diffusion.

 Such a latch is widely used in standard cell applications.

11: Sequential Circuits 23

 Conventional CMOS Flip-Flops

 Flip-flop is built as pair of back-to-back latches

11: Sequential Circuits 26

 Conventional CMOS Flip-Flops (1):
Dynamic Inverting Flip-flop

 
X
D Q

 

 Figure shows a dynamic

 inverting
 flip-flop builtQfrom a
pair of back-to-back
D
dynamic
X latches. Q
 
 Either the first or the last inverter can be removed to
reduce delay at the expense of greater noise sensitivity on the
unbuffered input or output.  

11: Sequential Circuits 27

 Conventional CMOS Flip-Flops (2):
Noninverting Static Flip-flop

 It adds feedback and another inverter to produce a

noninverting static flip-flop.

The PowerPC 603 microprocessor datapath used this flip-

flop design.

11: Sequential Circuits 28

 CMOS Flip-Flop Clocks

 Flip-flops usually take a single clock signal and locally

generate its complement.

 If the clock rise/fall time is very slow, it is possible that

both the clock and its complement will simultaneously be at
intermediate voltages, making both latches transparent.
11: Sequential Circuits 29
 CMOS Flip-Flop Clocks:
Two-phase Nonoverlapping Clocks

 A reasonable alternative is to use a pair of two-phase

nonoverlapping clocks instead of the clock and its complement.

 By making the nonoverlap large enough, the circuit will work

despite large skews.
11: Sequential Circuits 30
 CMOS Flip-Flop Clocks:
Two-phase Nonoverlapping Clocks

Flip-flop with two-phase nonoverlapping clocks

11: Sequential Circuits 31

 Two-phase Nonoverlapping Clock
Created from a Master Clock

 A very simple arrangement using combinational logic and

generating a two-phase clock at the frequency of a single-
phase input clock is set out in the figure.
11: Sequential Circuits 32
 Two-phase Nonoverlapping Clock
Created from a Master Clock

11: Sequential Circuits 33

Resettable Latches and Flip-Flops

 Force output low when reset asserted

11: Sequential Circuits 34

Resettable Latches and Flip-Flops

 There are two types of reset: synchronous and

asynchronous.
 Asynchronous reset forces Q low immediately.
 Synchronous reset waits for the clock.

11: Sequential Circuits 35

 Latch with Synchronous Reset

11: Sequential Circuits 36

 Flip-Flop with Synchronous Reset

11: Sequential Circuits 37

 Latch with Asynchronous Reset

11: Sequential Circuits 38

 Flip-Flop with Asynchronous Reset

11: Sequential Circuits 39

 Sequencing Methods
Tc

 Flip-flops

Flip-Flops
clk

 2-Phase Latches clk clk

 Pulsed Latches

Flop

Flop
Combinational Logic

2-Phase Transparent Latches

1
tnonoverlap tnonoverlap
Tc/2
2

1 2 1

Latch

Latch

Latch
Combinational Combinational
Logic Logic
Half-Cycle 1 Half-Cycle 1
Pulsed Latches

p tpw

p p
Latch

Latch
Combinational Logic

11: Sequential Circuits 43

 Sequencing with Flip-flops

 The token is captured in the first flip-flop on the first rising

edge of the clock.
 It propagates through the combinational logic and reaches the
second flip-flop on the second rising edge of the clock.
 The clock period is Tc.
11: Sequential Circuits 44
Sequencing with 2-Phase Latches

 The flip-flop can be viewed as a pair of back-to-back latches using

clk and its complement.
 If we separate the latches, we can divide the full cycle of
combinational logic into two phases, sometimes called half-cycles.
 The two latch clocks are often called ϕ1 and ϕ2.
11: Sequential Circuits 45
 Sequencing with Pulsed Latches

 Pulsed latch systems eliminate one of the latches from each cycle and
apply a brief pulse to the remaining latch.

 If the pulse is shorter than the delay through the combinational logic,
we can still expect that a token will only advance through one clock
cycle on each pulse.
11: Sequential Circuits 46
 Timing Diagrams

tpd Logic Prop. Delay

A tpd
Combinational
A Y
tcd Logic Cont. Delay Logic
Y tcd

tpcq Latch/Flop Clk->Q Prop. Delay

clk tsetup
tccq Latch/Flop Clk->Q Cont. Delay clk thold

Flop
D Q D
tpdq Latch D->Q Prop. Delay
tpcq

tcdq Latch D->Q Cont. Delay Q tccq

tsetup Latch/Flop Setup Time clk tsetup thold

clk
tccq tpcq
Thold Latch/Flop Hold Time
Latch

D Q D tpdq
tcdq
Q

11: Sequential Circuits 47

 Timing Diagram (Logic)

 Figure shows the response of combinational logic to the input

A changing from one arbitrary value to another.

 The output Y cannot change instantaneously. After the

contamination delay tcd , Y may begin to change or glitch.

 After the propagation delay tpd, Y must have settled to a final

value.
11: Sequential Circuits 48
 Timing Diagram (FF)

 Figure shows the response of a flip-flop. The data input must be stable for
some window around the rising edge of the flop if it is to be reliably sampled.

 The input D must have settled by some setup time (tsetup) before the rising
edge of clk and should not change again until a hold time (thold) after the clock
edge.

The output begins to change after a clock-to-Q contamination delay (tccq) and
completely settles after a clock-to-Q propagation delay (tpcq).
11: Sequential Circuits 49
 Timing Diagram (Latch)

 Figure shows the response of a latch.

The output initially changes tccq after the latch becomes

transparent on the rising edge of the clock and settles by tpcq .

While the latch is transparent, the output will continue to track

the input after some D-to-Q delay tcdq and tpdq .
11: Sequential Circuits 50
 Max-Delay Constraint: Flip-Flops
 The clock period
must be at least clk clk

Q1 D2

F1

F2
Combinational Logic

Tc

 Alternatively, the clk

tsetup
tpcq
maximum allowable
logic delay Q1 tpd

t pd  Tc   tsetup  t pcq  D2

sequencing overhead

11: Sequential Circuits 53

 Example 1

11: Sequential Circuits 54

 Example 1

11: Sequential Circuits 56

 Example 1

 The propagation delays and contamination delays of the path are given.
Suppose the registers are built from flip-flops with a setup time of 62 ps, hold
time of –10 ps, propagation delay of 90 ps, and contamination delay of 75 ps.
Calculate the minimum cycle time Tc at which the ALU self-bypass path will
operate correctly.

11: Sequential Circuits 57

 Example 1

critical path

11: Sequential Circuits 58

 Example 1

 The logic critical path involves propagation delays through the adder, result
mux, middle bypass mux, late bypass mux, and two 2-mm wires.

 Total propagation delay

tpd = tadder + tresult mux + tmiddle bypass mux + tlate bypass mux + 2*t2-mm

= 590 + 60 + 80 + 70 + 2*100
= 1000 ps.
11: Sequential Circuits 59
 Example 1

 Calculate the minimum cycle time Tc at which the ALU self-bypass path will
operate correctly.

 The cycle time Tc must be at least 90 + 1000 + 62 = 1152 ps.

11: Sequential Circuits 61

 Max-Delay Constraint: 2-Phase Latches

 The clock period 1 2 1

must be at least D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
Logic 1 Logic 2

1

 The maximum 2

allowable logic delay Tc

2
t 
D1 tpdq1
t pd  t pd 1  t pd 2  Tc 
pdq

sequencing overhead Q1 tpd1

D2 tpdq2

Q2 tpd2

D3

11: Sequential Circuits 63

 Max-Delay Constraint: Pulsed Latches

 The clock period p p

must be at least D1 Q1 D2 Q2

L1

L2
Combinational Logic

Tc

D1 tpdq

(a) tpw > tsetup

 The maximum Q1 tpd

allowable logic delay D2

t pd  Tc  max  t pdq , t pcq  tsetup  t pw 

p

 tpcq Tc tpw

sequencing overhead Q1 tpd tsetup

(b) tpw < tsetup
D2

11: Sequential Circuits 64

 Example 2

 Recompute the ALU self-bypass path cycle time if the flip-flop is replaced with
a pulsed latch. The pulsed latch has a pulse width of 150 ps, a setup time of 40
ps, a hold time of 5 ps, a clk-to-Q propagation delay of 82 ps and
contamination delay of 52 ps, and a D-to-Q propagation delay of 92 ps.

11: Sequential Circuits 65

 Example 2

 The logic propagation delay remains the same (adder, result mux, middle
bypass mux, late bypass mux, and two 2-mm wires).

 tpd = tadder + tresult mux + tmiddle bypass mux + tlate bypass mux + 2*t2-mm

 tpd is still 1000 ps.

11: Sequential Circuits 66

 Example 2

pulse width of 150 ps

 To recompute the path cycle time setup time of 40 ps
hold time of 5 ps
clk-to-Q propagation delay of 82 ps
 contamination delay of 52 ps
D-to-Q propagation delay of 92 ps

 The cycle time must be at least

92 + 1000 = 1092 ps.
11: Sequential Circuits 68
 Min-Delay Constraint: Flip-Flops
clk
 The minimum Q1

F1
CL
logic contamination
Delay
clk

D2

F2
tcd  thold  tccq clk

Q1 tccq tcd

D2 thold

11: Sequential Circuits 71

 Example 3

 In the ALU self-bypass example with flip-flops, the earliest input to the late
bypass multiplexer is the imm value coming from another flip-flop.
 Will this path experience any hold-time failures?

11: Sequential Circuits 72

 Example 3

 The late bypass mux has tcd = 45 ps.

 The flip-flops have thold = –10 ps and tccq = 75 ps.

11: Sequential Circuits 73

 Example 3

 tcd  thold  tccq

 tcd = 45 ps.

 thold – tccq = –10 – 75 = –85 ps.

 The eq. is easily satisfied. So, it will not experience hold-time failure.

11: Sequential Circuits 75

Min-Delay Constraint: 2-Phase Latches

 The minimum 1

Q1
logic contamination

L1
CL

Delay
2

D2
tcd 1,tcd 2  thold  tccq  tnonoverlap

L2
tnonoverlap
1

tccq
2

Q1 tcd

D2 thold

11: Sequential Circuits 77

 Min-Delay Constraint: Pulsed Latches

p
 The minimum
Q1
logic contamination

L1
CL

Delay
p

D2
tcd  thold  tccq  t pw

L2
p
tpw
thold

Q1 tccq tcd

D2

11: Sequential Circuits 78

 Time Borrowing
 In a flop-based system:
– Data launches on one rising edge
– Must setup before next rising edge
– If it arrives late, system fails
– If it arrives early, time is wasted
– Flops have hard edges
 In a latch-based system
– Data can pass through latch while transparent
– Long cycle of logic can borrow time into next
– As long as each loop completes in one cycle

11: Sequential Circuits 83

Time Borrowing Example
1

2
1 2 1
Latch

Latch

Latch
Combinational
(a) Combinational Logic
Logic

Borrowing time across Borrowing time across

half-cycle boundary pipeline stage boundary
1 2
Latch

Combinational Logic Latch Combinational

(b) Logic

Loops may borrow time internally but must complete within the cycle

11: Sequential Circuits 84

 How Much Borrowing?
2-Phase Latches 1 2

 c   tsetup  tnonoverlap 
D1 Q1 D2 Q2
T

L1

L2
Combinational Logic 1
tborrow
2
1

2 tnonoverlap
Pulsed Latches Tc

tsetup
tborrow  t pw  tsetup Tc/2
Nominal Half-Cycle 1 Delay
tborrow

D2

11: Sequential Circuits 85

 Clock Skew
 We have assumed zero clock skew
 Clocks really have uncertainty in arrival time
– Decreases maximum propagation delay
– Increases minimum contamination delay
– Decreases time borrowing

11: Sequential Circuits 90

 Skew: Flip-Flops
clk clk

t pd  Tc   t pcq  tsetup  tskew 

Q1 D2

F1

F2
Combinational Logic

   Tc

sequencing overhead
clk

tcd  thold  tccq  tskew

tpcq
tskew

Q1 tpdq tsetup

D2

clk

Q1

F1
CL

clk

D2

F2
tskew

clk
thold

Q1 tccq

D2 tcd

11: Sequential Circuits 92

 Skew: Latches
2-Phase Latches 1 2 1

2
t 
D1 Q1 Combinational D2 Q2 Combinational D3 Q3

L1

L2

L3
t pd  Tc  Logic 1 Logic 2

pdq

sequencing overhead 1

tcd 1 , tcd 2  thold  tccq  tnonoverlap  tskew 2

  tsetup  tnonoverlap  tskew 

Tc
tborrow 
2
Pulsed Latches
t pd  Tc  max  t pdq , t pcq  tsetup  t pw  tskew 

sequencing overhead

tcd  thold  t pw  tccq  tskew

tborrow  t pw   tsetup  tskew 

11: Sequential Circuits 93

 Synchronizers
 Sequencing elements are characterized by their setup
and hold time.

 If the data changes during the aperture between the

setup and hold times, the output may be unpredictable.

11: Sequential Circuits 94

 Synchronizers

 Properly designed synchronous circuits guarantee the

data is stable during the aperture.

 But systems may interface with data coming from

sources that are not synchronized to the same clock.

11: Sequential Circuits 95

 Synchronizers

 A synchronizer is a circuit that accepts an input that can

change at arbitrary times and produces an output aligned
to the synchronizer’s clock.

11: Sequential Circuits 96

 Metastability
 A latch is a bistable device. It has two stable states (0 and 1).

 Under the right conditions, that latch can enter a metastable

state in which the output is at an indeterminate level between 0
and 1.

11: Sequential Circuits 97

 Metastability

 Figure shows a simple model for a static latch consisting of two

switches (transmission gates) and two inverters.

 While the latch is transparent, the sample switch is closed and

the hold switch open.

 When the latch goes opaque, the sample switch opens and the
hold switch closes.
11: Sequential Circuits 98
 Metastability
 The stable states are
A = B = 0 and A = B = VDD.

 The metastable state is

A = B = Vm, where Vm is
an invalid logic level.

 This point is called

metastable because the
voltages are self-consistent
and may remain there
indefinitely. However, any
noise or other disturbance
may cause A and B to
switch to one of the two
stable states.
11: Sequential Circuits 99
 A Simple Synchronizer

 Figure shows a simple synchronizer built from a pair of flip-

flops.

11: Sequential Circuits 100

 A Simple Synchronizer

 F1 samples the asynchronous input D. The output X may be

metastable for some time, but will settle to a good level with high
probability if we wait long enough.

 F2 samples X and produces an output Q that should be a valid logic

level and be aligned with the clock.

 The synchronizer has a latency of one clock cycle, Tc .

11: Sequential Circuits 101