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Ref: Weste-Harris
Outline
Power and Energy
Dynamic Power
Static Power
VR2 t
PR t I R2 t R
R
dV
EC I t V t dt C V t dt
0 0
dt
VC
C V t dV 12 CVC2
0
dV C V
CLVDD 2
L DD
0
VDD
Tfsw CVDD VDD
T iDD(t)
fsw
CVDD 2 f sw
C
Dynamic power:
Pswitching a CVDD 2 f
Pswitching a CVDD 2 f
P
switching a CV 2
DD f
Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency
– Subthreshold leakage
• Normal Vt: 100 nA/mm
• High Vt: 10 nA/mm
• High Vt used in all memories and in 95% of logic gates
– Gate leakage 5 nA/mm
– Junction leakage negligible
Whigh-Vt 50 106 12l 0.95 950 106 4l 0.025m m / l 109.25 106 m m
I gate Wnormal-Vt Whigh-Vt 5 nA/m m / 2 275 mA
Pstatic 584 mA 275 mA 1.0 V 859 mW