Lecture 5:

Power
 Outline
 Power and Energy
 Dynamic Power
 Static Power

7: Power CMOS VLSI Design 4th Ed. 2

 Power and Energy
 Power is drawn from a voltage source attached to
the VDD pin(s) of a chip.

 Instantaneous Power: P (t )  I (t )V (t )
T

 Energy: E   P (t )dt
0
T
 Average Power: E 1
Pavg    P (t )dt
T T 0

7: Power CMOS VLSI Design 4th Ed. 3

 Power in Circuit Elements
PVDD t   I DD t VDD

VR2 t 
PR t    I R2 t  R
R

 
dV
EC   I t V t  dt   C V t  dt
0 0
dt
VC

 C  V t dV  12 CVC2
0

7: Power CMOS VLSI Design 4th Ed. 4

 Charging a Capacitor
 When the gate output rises
– Energy stored in capacitor is
2
EC  12 CLVDD
– But energy drawn from the supply is
 
dV
EVDD   I t VDD dt   C L VDD dt
0 0
dt
VDD

 dV  C V
2
 CLVDD L DD
0

– Half the energy from VDD is dissipated in the pMOS

transistor as heat, other half stored in capacitor
 When the gate output falls
– Energy in capacitor is dumped to GND
– Dissipated as heat in the nMOS transistor

7: Power CMOS VLSI Design 4th Ed. 5

 Switching Waveforms
 Example: VDD = 1.0 V, CL = 150 fF, f = 1 GHz

7: Power CMOS VLSI Design 4th Ed. 6

 Switching Power
T
1
Pswitching   iDD (t )VDD dt
T 0
T
VDD

T 0 iDD (t )dt

VDD
 Tfsw CVDD  VDD
T iDD(t)
fsw

 CVDD 2 f sw
C

7: Power CMOS VLSI Design 4th Ed. 7

 Activity Factor
 Suppose the system clock frequency = f
 Let fsw = f, where  = activity factor
– If the signal is a clock,  = 1
– If the signal switches once per cycle,  = ½

 Dynamic power:
Pswitching   CVDD 2 f

7: Power CMOS VLSI Design 4th Ed. 8

 Short Circuit Current
 When transistors switch, both nMOS and pMOS
networks may be momentarily ON at once
 Leads to a blip of “short circuit” current.
 < 10% of dynamic power if rise/fall times are
comparable for input and output
 We will generally ignore this component

7: Power CMOS VLSI Design 4th Ed. 9

Power Dissipation Sources
 Ptotal = Pdynamic + Pstatic
 Dynamic power: Pdynamic = Pswitching + Pshortcircuit
– Switching load capacitances
– Short-circuit current
 Static power: Pstatic = (Isub + Igate + Ijunct + Icontention)VDD
– Subthreshold leakage
– Gate leakage
– Junction leakage
– Contention current

7: Power CMOS VLSI Design 4th Ed. 10

Dynamic Power Example
 1 billion transistor chip
– 50M logic transistors
• Average width: 12 
• Activity factor = 0.1
– 950M memory transistors
• Average width: 4 
• Activity factor = 0.02
– 1.0 V 65 nm process
– C = 1 fF/m (gate) + 0.8 fF/m (diffusion)
 Estimate dynamic power consumption @ 1 GHz.
Neglect wire capacitance and short-circuit current.

7: Power CMOS VLSI Design 4th Ed. 11

 Solution
Clogic  50 106  12  0.025 m /  1.8 fF /  m   27 nF
Cmem  950 106   4  0.025 m /  1.8 fF /  m   171 nF

Pdynamic  0.1Clogic  0.02Cmem  1.0  1.0 GHz   6.1 W

2

7: Power CMOS VLSI Design 4th Ed. 12

 Dynamic Power Reduction
2
P
 switching   CVDD f

 Try to minimize:
– Activity factor
– Capacitance
– Supply voltage
– Frequency

7: Power CMOS VLSI Design 4th Ed. 13

 Static Power
 Static power is consumed even when chip is
quiescent.
– Leakage draws power from nominally OFF
devices
– Ratioed circuits burn power in fight between ON
transistors

7: Power CMOS VLSI Design 4th Ed. 14