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  • Lecture11 DRAM

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    Ismat Jahan
    27 views9 pages
    This document summarizes key concepts about DRAM (Dynamic Random Access Memory). It discusses the basic components of a DRAM cell including a capacitor and switch. It also outlines the write and read sequences for DRAM, noting that writing involves activating the wordline to store a bit value in the capacitor, while reading involves activating the wordline and checking the bit value on the bitline. Finally, it provides a diagram illustrating the layout of components in a DRAM cell including the capacitor, switch, wordline, bitline, and connections to voltage sources.

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    This document summarizes key concepts about DRAM (Dynamic Random Access Memory). It discusses the basic components of a DRAM cell including a capacitor and switch. It also outlines the write and read sequences for DRAM, noting that writing involves activating the wordline to store a bit value in the capacitor, while reading involves activating the wordline and checking the bit value on the bitline. Finally, it provides a diagram illustrating the layout of components in a DRAM cell including the capacitor, switch, wordline, bitline, and connections to voltage sources.

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    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    27 views9 pages

    Lecture11 DRAM

    Uploaded by

    Ismat Jahan
    This document summarizes key concepts about DRAM (Dynamic Random Access Memory). It discusses the basic components of a DRAM cell including a capacitor and switch. It also outlines the write and read sequences for DRAM, noting that writing involves activating the wordline to store a bit value in the capacitor, while reading involves activating the wordline and checking the bit value on the bitline. Finally, it provides a diagram illustrating the layout of components in a DRAM cell including the capacitor, switch, wordline, bitline, and connections to voltage sources.

    Copyright:

    © All Rights Reserved
    Download as PPTX, PDF, TXT or read online from Scribd
    Flag for inappropriate content
    of 9

    Lecture 11

    August 23, 2021


    Test Test Test
    Test
    +++ +++
    C ----- 5V 5V +++
    0V 5V C ----- 5V
    C 5V -----
    5V C
    DRAM - Dynamic random-access
    Test
    memory
    C
    0V 5V

    0V
    5V
    0V

    Test 0V 0V
    5V
    DRAM - Dynamic random-access memory
    wordline

    bittest

    bitline

    VSS
    Number of Byte=number of row=4byte
    Number of bit=number of column=8bit
    Test Test Test Test
    +++ +++
    C 5V +++
    0V 5V
    ----- C ----- C5V ----- C5V
    write 5V 5V

    • Sequence
    • Make bitline 1 or 0
    • Make wordline 1 bittest bittest
    • Keep wordline 1 for a short duration
    • Make wordline 0
    • Check saved data at bittest
    Capacitor will take the value of bitline only at gate pulse or wordline pulse
    read
    • Sequence
    • Make bittest 1 or 0
    • Make wordline 1 bittest bittest
    • Keep wordline 1 for a short duration
    • Make wordline 0
    • Check test data at bitline
    G D G
    S S D

    blue = metal1
    white = contact
    Cap Switch
    green=poly
    B B

    wordline

    Cap Switch
    G
    bittest S D
    B
    G bitline
    S D
    B

    VSS
    wordline

    G G
    S S
    D D
    bittest
    bitline
    Cap
    Switch

    VSS
    B B

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