MOS

Transistor
Theory
1
 Outline
 Introduction
 MOS Capacitor
 nMOS I-V Characteristics
 pMOS I-V Characteristics
 Gate and Diffusion Capacitance

CMOS VLSI Design 4th Ed. 2

 Introduction
 So far, we have treated transistors as ideal switches
 An ON transistor passes a finite amount of current
– Depends on terminal voltages
– Derive current-voltage (I-V) relationships
 Transistor gate, source, drain all have capacitance
– I = C (V/t) -> t = (C/I) V
– Capacitance and current determine speed

CMOS VLSI Design 4th Ed. 3

 MOS Capacitor
 Gate and body form MOS
capacitor polysilicon gate
V <0
 Operating modes +
g
silicon dioxide insulator

- p-type body
– Accumulation
– Depletion (a)

– Inversion 0<V <V g t

depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

CMOS VLSI Design 4th Ed. 4

 Terminal Voltages
 Mode of operation depends on Vg, Vd, Vs Vg

+ +
– Vgs = Vg – Vs Vgs Vgd
- -
– Vgd = Vg – Vd
Vs Vd
-
– Vds = Vd – Vs = Vgs - Vgd Vds +
 Source and drain are symmetric diffusion terminals
– By convention, source is terminal at lower voltage
– Hence Vds  0
 nMOS body is grounded. First assume source is 0 too.
 Three regions of operation
– Cutoff
– Linear
– Saturation
CMOS VLSI Design 4th Ed. 5
 nMOS Cutoff
 No channel
 Ids ≈ 0

Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

CMOS VLSI Design 4th Ed. 6

 nMOS Linear
 Channel forms
 Current flows from d to s
V > Vt
– e from s to d Vgd = Vgs
gs
- + g +
- -
 Ids increases with Vds s d
Vds = 0
n+ n+

 Similar to linear resistor p-type body

b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed. 7

 nMOS Saturation
 Channel pinches off
 Ids independent of Vds
 We say current saturates
 Similar to current source

Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed. 8

 I-V Characteristics
 In Linear region, Ids depends on
– How much charge is in the channel?
– How fast is the charge moving?

CMOS VLSI Design 4th Ed. 9

 Channel Charge
 MOS structure looks like parallel plate capacitor
while operating in inversions
– Gate – oxide – channel
 Qchannel = CV
 C = Cg = oxWL/tox = CoxWL Cox = ox / tox
 V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source Vgs Cg Vgd drain
W
Vs - - Vd
channel
tox n+ - + n+
SiO2 gate oxide
Vds
L
n+ n+ (good insulator, ox = 3.9) p-type body
p-type body

CMOS VLSI Design 4th Ed. 10

 Carrier velocity
 Charge is carried by e-
 Electrons are propelled by the lateral electric field
between source and drain
– E = Vds/L
 Carrier velocity v proportional to lateral E-field
– v = E  called mobility
 Time for carrier to cross channel:
– t=L/v

CMOS VLSI Design 4th Ed. 11

 nMOS Linear I-V
 Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds 
t
W  V  V  Vds V
 Cox  gs t  ds
L 2 
V W
  Vgs  Vt  ds Vds  = Cox
 2 L

CMOS VLSI Design 4th Ed. 12

 nMOS Saturation I-V
 If Vgd < Vt, channel pinches off near drain
– When Vds > Vdsat = Vgs – Vt
 Now drain voltage no longer increases current
 Vdsat V
I ds   Vgs  Vt   dsat
 2 

 Vgs  Vt 
2

CMOS VLSI Design 4th Ed. 13

 nMOS I-V Summary
 Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds     Vgs  Vt   ds linear
 2 
ds dsat

 
Vgs  Vt 
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed. 14

 Example
 We will be using a 0.6 m process for your project
– From AMI Semiconductor
– tox = 100 Å 2.5
Vgs = 5
–  = 350 cm2/V*s 2

– Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
 Plot Ids vs. Vds 1
Vgs = 3

– Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
Vgs = 1
– Use W/L = 4/2  0
0 1 2 3 4 5
W  3.9  8.85 1014   W W Vds

   Cox  350   8    120 μA/V 2
L  100 10  L  L

CMOS VLSI Design 4th Ed. 15

 pMOS I-V
 All dopings and voltages are inverted for pMOS
– Source is the more positive terminal
 Mobility p is determined by holes
– Typically 2-3x lower than that of electrons n
– 120 cm2/V•s in AMI 0.6 m process 0
Vgs = -1

 Thus pMOS must be wider to -0.2

Vgs = -2

Vgs = -3

provide same current

Ids (mA)
-0.4

– In this class, assume Vgs = -4

-0.6
n / p = 2
Vgs = -5
-0.8
-5 -4 -3 -2 -1 0
Vds

CMOS VLSI Design 4th Ed. 16

 Capacitance
 Any two conductors separated by an insulator have
capacitance
 Gate to channel capacitor is very important
– Creates channel charge necessary for operation
 Source and drain have capacitance to body
– Across reverse-biased diodes
– Called diffusion capacitance because it is
associated with source/drain diffusion

CMOS VLSI Design 4th Ed. 17

 Gate Capacitance
 Approximate channel as connected to source
 Cgs = oxWL/tox = CoxWL = CpermicronW
 Cpermicron is typically about 2 fF/m

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, ox = 3.90)
p-type body

CMOS VLSI Design 4th Ed. 18

 Diffusion Capacitance
 Csb, Cdb
 Undesirable, called parasitic capacitance
 Capacitance depends on area and perimeter
– Use small diffusion nodes
– Comparable to Cg
for contacted diff
– ½ Cg for uncontacted
– Varies with process

CMOS VLSI Design 4th Ed. 19