Lecture 3:

CMOS Transistor
Theory
Outline
• Introduction
• MOS Capacitor
• nMOS I-V Characteristics
• pMOS I-V Characteristics
• Gate and Diffusion Capacitance

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 2
Introduction
• So far, we have treated transistors as ideal switches
• An ON transistor passes a finite amount of current
• Depends on terminal voltages
• Derive current-voltage (I-V) relationships
• Transistor gate, source, drain all have capacitance
• I = C (DV/Dt) -> Dt = (C/I) DV
• Capacitance and current determine speed

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 3
MOS Capacitor
• Gate and body form MOS capacitor
• Operating modes polysilicon gate
Vg < 0
• Accumulation +
silicon dioxide insulator
p-type body
-
• Depletion
• Inversion (a)

0 < Vg < Vt
depletion region
+
-

(b)

Vg > Vt
inversion region
+
- depletion region

(c)

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 4
Terminal Voltages
Vg
• Mode of operation depends on Vg, Vd, Vs + +
Vgs Vgd
• Vgs = Vg – Vs - -
• Vgd = Vg – Vd Vs Vd
- +
• Vds = Vd – Vs = Vgs - Vgd Vds

• Source and drain are symmetric diffusion terminals

• By convention, source is terminal at lower voltage
• Hence Vds  0
• nMOS body is grounded. First assume source is 0 too.
• Three regions of operation
• Cutoff
• Linear
• Saturation
CMOS VLSI Design 4th Ed.
3: CMOS Transistor Theory 5
nMOS Cutoff
• No channel
• Ids ≈ 0
Vgs = 0 Vgd
+ g +
- -
s d

n+ n+

p-type body
b

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 6
nMOS Linear
• Channel forms
• Current flows from d to s Vgs > Vt
+ g +
Vgd = Vgs

- -
• e- from s to d s d
Vds = 0
• Ids increases with Vds
n+ n+

p-type body

• Similar to linear resistor b

Vgs > Vt
Vgs > Vgd > Vt
+ g +
- - Ids
s d
n+ n+
0 < Vds < Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 7
nMOS Saturation
• Channel pinches off
• Ids independent of Vds
• We say current saturates
• Similar to current source
Vgs > Vt
g Vgd < Vt
+ +
- -
s d Ids

n+ n+
Vds > Vgs-Vt
p-type body
b

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 8
I-V Characteristics
• In Linear region, Ids depends on
• How much charge is in the channel?
• How fast is the charge moving?

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 9
Channel Charge
• MOS structure looks like parallel plate capacitor while operating in
inversions
• Gate – oxide – channel
• Qchannel = CV Cox = eox / tox

• C = Cg = eoxWL/tox = CoxWL
• V = Vgc – Vt = (Vgs – Vds/2) – Vt
gate
Vg
polysilicon + +
gate source V gs
Cg
V gd drain
W - -
Vs channel Vd

eox =electric permittivity of oxide

tox n+ - + n+
Vds
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9) p-type body
p-type body
tox =oxide thickness

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 10
Carrier velocity
• Charge is carried by e-
• Electrons are propelled by the lateral electric field between source
and drain
• E = Vds/L
• Carrier velocity v proportional to lateral E-field
• v = mE m called mobility
• Time for carrier to cross channel:
• t=L/v

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 11
nMOS Linear I-V
• Now we know
• How much charge Qchannel is in the channel
• How much time t each carrier takes to cross
Qchannel
I ds =
t
= mCox
W V − V − Vds V
 gs  ds
 2 
t
L

=  Vgs − Vt −
Vds   = mCox
W
Vds
 2  L

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 12
nMOS Saturation I-V
• If Vgd < Vt, channel pinches off near drain
• When Vds > Vdsat = Vgs – Vt
• Now drain voltage no longer increases current

I ds =  Vgs − Vt −
Vdsat 
 Vdsat
 2

( − Vt )
2
= Vgs
2

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 13
nMOS I-V Summary
• Shockley 1st order transistor models


 0 Vgs  Vt cutoff

  Vds V V  V
I ds =   Vgs − Vt −  ds linear
 2 
ds dsat

 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 14
Example
• We will be using a 0.6 mm process for your project
• From AMI Semiconductor
• tox = 100 Å 2.5
Vgs = 5

• m = 350 cm2/V*s 2

• Vt = 0.7 V 1.5 Vgs = 4

Ids (mA)
• Plot Ids vs. Vds 1
Vgs = 3
• Vgs = 0, 1, 2, 3, 4, 5 0.5
Vgs = 2
• Use W/L = 4/2 l 0
Vgs = 1
0 1 2 3 4 5
W  3.9  8.85 10−14   W  W Vds
 = mCox = ( 350 )  −8   = 120 μA/V 2
L  100 10  L  L

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 15
pMOS I-V
• All dopings and voltages are inverted for pMOS
• Source is the more positive terminal
• Mobility mp is determined by holes
• Typically 2-3x lower than that of electrons mn
• 120 cm2/V•s in AMI 0.6 mm process 0
Vgs = -1
Vgs = -2

• Thus pMOS must be wider to -0.2

Vgs = -3

provide same current

Ids (mA)
-0.4
Vgs = -4

• In this class, assume -0.6

mn / mp = 2 -0.8
Vgs = -5
-5 -4 -3 -2 -1 0
Vds

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 16
Capacitance
• Any two conductors separated by an insulator have capacitance
• Gate to channel capacitor is very important
• Creates channel charge necessary for operation
• Source and drain have capacitance to body
• Across reverse-biased diodes
• Called diffusion capacitance because it is associated with source/drain
diffusion

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 17
Gate Capacitance
• Approximate channel as connected to source
• Cgs = eoxWL/tox = CoxWL = CpermicronW
• Cpermicron is typically about 2 fF/mm

polysilicon
gate
W
tox
L SiO2 gate oxide
n+ n+ (good insulator, eox = 3.9e0)
p-type body

CMOS VLSI Design 4th Ed.

3: CMOS Transistor Theory 18