MOS Transistor

Theory
IIIT Hyderabad
Asst. Prof. A. Sarje
 available as thin flat circular wafers of 15–30 cm in diameter. CMOS technology provides
two types of transistors (also called devices): an n-type transistor (nMOS) and a p-type
transistor (pMOS). Transistor operation is controlled by electric fields so the devices are

NMOS
also called Metal Oxide Semiconductor Field Effect Transistors (MOSFETs) or simply
FETs. Cross-sections and symbols of these transistors are shown in Figure 1.9. The n+
and p+ regions indicate heavily doped n- or p-type silicon.

Source Gate Drain Source Gate Drain

Polysilicon

SiO2

Basic Planar transistor

n+ n+ p+ p+

p bulk Si n bulk Si

NMOS
(a) (b)
• Gate oxide & Poly silicon gate —> Controls channel
FIGURE 1.9 nMOS transistor (a) and pMOS transistor (b)
formation
• Source/Drain —> doped n+ region: determine current flow
• Body —> p-substrate (p-sub)
• P-n junctions exist between n+ and p-sub (revise p-n junctions)
• Distance between S and D is well edge is the channel length ‘L’
• *Drawn channel length is slightly bigger than the actual channel length. Why?

POSD Dr. A. Sarje

 NMOS

Enhancement mode NMOS

NMOS
W is the width of the transistor
Low resistance connection exists for S/D/B/G: higher doped tubs
Typically L = 0.1 to 3 mm, W = 0.2 to 100 mm, and the thickness of the oxide layer (tox) is in the range of 2 to 50 nm.

POSD Ref: Weste; Serra & Smith Dr. A. Sarje

 Energy Band Diagram

POSD FScD Pierret Dr. A. Sarje

 Energy Band Diagram

POSD FScD Pierret Dr. A. Sarje

 Block Charge Diagram

POSD FScD Pierret Dr. A. Sarje

 MOS characteristics 2.1

Vgs = 0 Vgd
+ g +
– –
s d
Cutoff:
n+ n+
No Channel
p-type body Ids = 0

b
(a)

• Vgs > Vt
Vgs=0; Vds=0 + g +
Vgd = Vgs
– –

•
s d
No conduction channel. Ids=0 Vds = 0
n+ n+

• What
(b)
happens when Vgs is decreased or increased?
p-type body
b
Linear:
Channel Formed
POSD Ref: Weste; Serra & Smith Ids Increases with Vds
Dr. A. Sarje
 Accumulation Vgs<0
r2 MOS Transistor Theory
Consider the Gate Bulk Region

Polysilicon Gate
Vg < 0
Silicon Dioxide Insulator
+
– p-type Body

(a)

• Vgs<0
0 < Vg < Vt
• Majority mobile carriers
+ in bulk accumulate under theDepletion
gate Region
–

• No conduction channel

• (b)
Cg is oxide capacitance Cox

POSD Ref: Weste; Serra & Smith Dr. A. Sarje

 Accumulation Band Diagram

N Body

• Note:

• Vg>0 => Metal EF lowers than the Semiconductor EF

• Electron density in Semiconductor

POSD FScD Pierret Dr. A. Sarje
 Depletion region
Vg < 0
Polysilicon Gate
Silicon Dioxide Insulator

Vgs>0 (small, <Vt)

+
– p-type Body

(a)

0 < Vg < Vt
Depletion Region
+
–

(b)

• Vgs>0
Vg > V t
• Positive mobile carriers
+ repelled away from the gate: depletion region formed
Inversion Region
Depletion Region
–

• Fixed acceptor negative ions remain behind

• (c)
No conduction channel
FIGURE 2.2 MOS structure demonstrating (a) accumulation, (b) depletion, and
• (c) inversion
Cg is the oxide capacitance + depletion region capacitance.
POSD Ref: Weste; Serra & Smith Dr. A. Sarje
 Depletion Band Diagram

• Note:

• Vg< 0 => Metal EF is higher than the Semiconductor EF

• Electron density in Semiconductor

POSD FScD Pierret Dr. A. Sarje
 (a)

0 < Vg < Vt Inversion region

+
Depletion Region

Vgs>Vt
–

(b)

Vg > V t
Inversion Region
+
Depletion Region
–

(c)
• Vgs>Vt
FIGURE 2.2 MOS structure demonstrating (a) accumulation, (b) depletion, and
(c) inversion

• Negative minority carriers attracted under the gate to form

voltage depends on the number of dopants in the body and the thickness tox of the oxide. It
Inversion
is usually positive, as channel
shown in this example, but can be engineered to be negative.
Figure 2.3 shows an nMOS transistor. The transistor consists of the MOS stack

•
between two n-type regions called the source and drain. In Figure 2.3(a), the gate-to-source
No current flow yet
voltage Vgs is less than the threshold voltage. The source and drain have free electrons. The
body has free holes but no free electrons. Suppose the source is grounded. The junctions
• Cg is
between theequal
body and
current flows.Ref:We
tothe Coxsource or drain are zero-biased or reverse-biased, so little or no
say the transistor is OFF, and this mode of operation is called cutoff. It is
POSD Weste; Serra & Smith Dr. A. Sarje
 Inversion Band Diagram

POSD FScD Pierret Dr. A. Sarje

 Inversion Band Diagram

POSD FScD Pierret Dr. A. Sarje

 Band Diagram
p-sub

POSD FScD Pierret Dr. A. Sarje

 Band Diagram

POSD FScD Pierret Dr. A. Sarje

 Threshold voltage

• The p-sub is ‘inverted’ to

n-type material and
inversion layer formed
from S to D
• Vgs value at which
enough electrons
accumulate to form a
conducting channel is
called threshold voltage
Vth~0.3-1.5V (technology
dependent)

POSD Ref: Weste; Serra & Smith Dr. A. Sarje

 n+ n+

Linear Region
p-type body
b
(a)

Vgs > Vt
Vgd = Vgs
+ g +
– –
s d
• Vgs>Vt; Vds<Vgs n+ n+ Vds = 0

p-type body
• Drain voltage small: (b) b
uniform depletion region
along the channel Vgs > Vt
Vgs > Vgd > Vt
+ g +

•
– –
Cox is evenly distributed s d
Ids
between Cgs and Cgd.
n+ n+
0 < Vds < Vg

• Cgs= Cgd=Cox/2 (c)

p-type body
b

Vgs > Vt
g Vgd < Vt
POSD Ref: Weste; Serra & Smith + Dr. A. Sarje +
 d

n+ n+ Vds = 0

Linear Region
(b)
p-type body
b
L
C
Vgs > Vt I
Vgs > Vgd > Vt
+ g +
– –
s Ids
d

• Vgs>Vt; Vds~Vgs n+ n+
0 < Vds < Vgs – Vt
p-type body

• Drain voltage
(c)
b

increases: variation in
depletion region along Vgs > Vt
g Vgd < Vt
+ +
the channel – –
s d Ids

• n+ n+
Vds > Vgs – Vt
S
C
p-type body I
(d) b

FIGURE 2.3 nMOS transistor demonstrating cutoff, linear, and saturation regions of
POSD Ref: Weste; Serra & Smith Dr. A. Sarje
 p-type body s Ids
d
(b)

Saturation region
b
Linear:
n+ n+
Channel Formed 0 < Vds < Vgs – Vt
Vgs > Vt Ids Increases with Vds
Vgs > Vgdp-type
> Vt body
+(c) g +
– – b
s Ids
d

n+ n+
Vgs > Vt 0 < Vds < Vgs – Vt
Vgd < Vt
• p-type body + g
Vgs>Vt; Vds>Vgs-Vt
(c)
b –
+
–
s d Ids

• Drain voltage increases:

V >V
+
gs
g
t
+
n+V < V n+ gd Vds > Vgs – Vt
t

channel is pinched off– –

p-type body
s d I ds
(charge carriers swept(d)
n+ n+
b Saturation:
off due to large electric p-type body V >V –V Channel Pinched Off
I Independent of V
ds gs t
ds ds

field) (d) FIGURE 2.3 bnMOS transistor demonstrating cutoff, linear, and saturation regions o

• FIGURE 2.3 nMOS transistor demonstrating cutoff, linear, and saturation regions of operation
Cox is taken up by Cgs resistive, triode, nonsaturated, or unsaturated; the current increases with
and Cgd is negligiblyage and gate voltage. If Vds becomes sufficiently large that Vgd < Vt
triode, nonsaturated, or unsaturated; the current increases with both the drain volt-
small. resistive, longer inverted near the drain and becomes pinched off (Figure 2.3(d))
age and gate voltage. If Vds becomes sufficiently large that Vgd < Vt , the channel is no
longer inverted near tion is still
the drain andbrought about off
becomes pinched by (Figure
the drift of electrons
2.3(d)). However, under
conduc-the influence
voltage.
tion is still brought about by theAs electrons
drift reach
of electrons underthe end of the
the influence channel,
of the they are injected
positive drain
• Cgs=2Cox /3 As electronsregion
voltage. near
reach the endthe drain
of the and accelerated
channel, toward
they are injected into thethedepletion
drain. Above this dr
region near the drainrent and Iaccelerated toward the drain. Above this drain voltage the cur-
ds is controlled only by the gate voltage and ceases to be influence
rent Ids is controlled only by the gate voltage and ceases to be influenced by the drain. This
mode
mode is called saturation.
is called saturation.
POSD Ref: Weste; Serra & Smith Dr. A. Sarje
 Each carrier modelv is=sec-
stant.in
Inthe channel is accelerated
we call t tothe
anequivalent
average velo
the long-channel,
latively low, which is ideal, no longer first-order,
the case in ornanometer
Shockley model.devices. ThisSubsequent E
transistor
enownin the
model
ofine
nnel form I-V Characteristic
as the
model a chan-
the model
is
tochannel
0.
long-channel,
reflect
lateral electric field,
assumes
these
high
the
to reflect
layer of SiO
A
Qchannel
i.e., the
typical
The
processes,
ideal,
channel
high
that
that
electric
is
fields,first-order,
field
hasbetween
leakage,
the samesource
thevalue and
fields, leakage,
C . In
current drain.
length
this
field
orand
case,The
of t
ox
for
through
E is
othermodel.
Shockley the
electrons
an OFF
voltage
Subsequent sec-
nonidealities.
and other nonidealities. E =
in
transistoran
difference
Vds ox
nMOS
is 0.
between drainSou
gate transistor with lo
polysilicon
a

OS
nsistor
urns ON
nsistor
drift from
Transistor
ng-channel
turns(V
Theory
model
ON
source
(
(Long Channel) )
ity is called theEach
gs >(V
assumesTheory
mobility.
Vt),> the
500
gs V –700
that
gatecm
the
Q2
attracts
current
/V
2
through
· s.carriers
However,
carrier in the channel is accelerated to an a
t), the gate
to drain
attracts
channel carriers
an
= C g(electrons)
OFF
V gc most
(electrons)
transistor
Vtot to
formform
transistors
is
a chan-
tox
0.L
a chan-
ox
today
=
Echannel
Vds(2.1)
W
operate at far hig
ox
Vs
ectrons drift The time
mobility
from source to Gate
drain isat severely
required a rate
at a rateproportional
for carriers
curtailed
proportional toto
(see
thethe
toSection
crossn+ the 2.4.1). is the chann
enbetween
d these regions.
isof2the
lateral electric field, i.e., the field
these regions. Thus,
capacitance Thus, wewe cancancompute
of the v = between
compute currents
gate E
to the
source and
currents ififwewe
channel and
L
L n+
is the
pter
Cg the
mount
f charge carrier
charge
in the
MOS
in the
channel
Transistor
The
velocity:
channel and
electric
andthe the L/v.
rate
rate
Theory
field
atat E is
Therefore,
which
which it
it
the
moves.
moves.
voltage
the Vp-type
difference
current gc BodyVbetween
between
Gate
t Gate drain
source andan s
nt ofSome nanometer
Some nanometer voltage ityprocesses
Model derivation: Long is called
attracting usethe
The
processes mobility.
Channel/Shockley/First
time
use a different
a different
charge required
to for
gate dielectric
gate dielectric
the order/Ideal
carriers
with a high
channel with tothe cross the required
channel istothe ch
the+charge
channel length thebeyond the minimum
V Q = CV. Thus,
hat the
charge amount
charge
onSource
each of
on each
plate plate
of aofcapacitor in
ga capacitor the channel
+ isisDrain
Q = CV. Thus, divided
the bySiO2 Gate time
Oxide
Vg cross
he
A• typical
channel Q
value isthe
of callfor carrier
t electrons velocity:
t theinequivalentanoxide
nMOS L/v. Therefore,
transistor wt the current between
V+g Drain sourc
(insulator,
Source ox = 3.9 0)
ed to
. Instant.
these
nel Qchannel is invert
Inprocesses,
these from
processes,
Channel
channel
we V p we
Charge to
call n. The
the equivalent
C V gate voltage
oxide
thickness is
(EOT),(E
thickness referenced to
Source
+
V the + chan- + Drain
gs g gd
ox v= E ox FIGURE 2.6 Transistor Vgsdimensions
Cg Vgd

( ·has )nanometer
ds V
hich is not Vs grounded. –amount 2 If of thecharge source
– in the
is at channel
V and
sQchannel divided
the drain E =by
is the
at V time
, the C–required
V toAvc
500of
oflayer
SiO –700 cmthat
SiOhas
that /V
the
Some s. However,
same theCsame . In•most
channel
Cthis . Intransistors
case,
processes thist case, atoday
V
is thinner
use is operate
thinner
thangate
tdifferent atdi
thethaacf –

( )
Qchannel = C g V gc Vt d (2.1) V dgs
channel g V gd
n+ oxI = Current n+V – L –
Crossing Charge
s d

ge is Vc = (Vchannel 2 Qn+ – 2
+ V = )/2
C V V = V V +
+
V /2. Therefore, ox
(2.1) the mean ox s differenceox
V
+ n+
channel – VVd
ds
Eachmobility isstant.
severely
s curtailed
d (see Section
s
an2.4.1).
ds
g gc t ds
Each in
carrier carrier
the in
A typical
the capacitance of the p-type Inthe
channel thesechannel
value
gate to Body
The ofis accelerated
isprocesses,
accelerated
ds
forwetoelectrons
call tothe
taverageaninequivalent
the channel and Vgc Vt is the
time required average
velocity,
foran nMOS veloci
carriers prt
L v toQchannel
v,oxid cross ox
the
n+p-type –
channel
Body V + n+
en the gate and channel potentials V is V
gc I dsg = c – V = V – V ds p-type is
/2, as the chann
ds
voltage
Theattracting
electric charge
field to
isthe
the channel
voltage beyond
difference the minimum
between drain gs Body FIGURE

( )
lateral
al electric
•
nattracting electric
in Figure
invert field,
pacitance of the the layerfield,
i.e.,
500
p to2.5.
from Voltage the
of
–700 i.e.,
field
SiO
gatecarrier
n. The across
E
cmthe
that
/Vfield
between
gate voltage·has
to the channel
s. between
source
the same
velocity:
However,
Gate- source
andC
most
2
is referenceddrain.
and. In
2Vand
L/v. drain.
The
this case,
V
transistors
gc
to the t The
is
Therefore, t isc
constant
the
chan- W the
today L vcurrent ox between source ox an
is itythe is
calledchannel
called
the
charge
length
the
tosource
the channel beyond theis at =Vd , the
minimum C oxdividedVAverage Vgatettime
to Vchannel2 Vds to cross
mobility. Each
amount
mobility.carrier in the
of channel
charge is accelerated
in the channel to an av by the potential:
required
( )
We s not grounded.
can Channel
model If the
the gate is at V and
asisareferenced the
parallel drain plate capacitor with gs capacitance ds proportiona
Vrom = (Vp to
+ Vn. mobility
The
Average
)/2 = Vgate
+gateVis severely
voltage
to
/2. • curtailed
channel
Therefore,
s
(see Section
potential:
the mean to 2.4.1).
the chan-
differencev=velocity=
L
C V
W
of
gc the
= (V gs carriers
V + V
V
)/2 = V
Vds 2 potential:
gs Vds/2
–
Vdsis t
(v E=theis Efield )
c s d s ds gd
ver thickness. lateralThe If the
electric gate
field,field
i.e., has length
between and
source andwidth and the oxide thickness
L
betd W
ounded. If the source is at V and the drain is at V , the ox Average gs gate t to channel
e gate and channel potentials Vsgc is Vg – Vc = Vgs – Vds /2,
electric
Vgc = (Vgs + Vgd)/2 = Vgs – Vds/2 the voltage
V difference = d asV Q FIGURE V L
2.52 V
Average gate to channel voltage ox
v E= = E I ds = GTchannel ds Vgc = ds(Vdsgs + Vgd)/2 = Vgs – Vds/2
+in
nigure )/2 = Vs 2.6,
VdFigure + Vdsthe capacitance
/2. Therefore,
( L )
theismean difference
2.5.
n model
and channel
FIGURE
itythe is
2.5
called
channel length
the gatepotentials
as aAverage the
parallelVplate mobility.
gate is capacitor
toV – V
channel =with
V capacitance
–
voltage V /2, as =L vVGTto Vds 2 Vds
proportional
ickness.where If the gate has length L and width W and the oxide thickness is tFIGURE
gc g c gs ds
, as 2.5 Average gate to channel vo
A •typical ( )
5. WL WL
ox
igure 2.6, theGate
pical value value
of for of capacitance
where for
electrons electrons
in an in
nMOS an nMOS
transistor transistor
with V low wit W
roportional capacitance
to
The time required for carriers
the gate as a parallel plate
is
• = kox 0 with=capacitance
C g capacitor to cross the channel v =
ox Ids=E = =proportional
is the c C ox
oxW WL(V gs toVt Vds 2) Vds ds (2
–700 500
ckness cm–700
If the is/V cm
·
gates. , as length2WL
tox2has
/V ·
However, s. However,
most most
transistors
L and width WL Wt and
transistors
today today
operate E =
operate
at
ox the oxide far t=ox thickness
at
higher C ox Lis; tVoxW
far , as = V gs V t
the carrier velocity: L/v. Therefore, the current between sourL GT
6, the capacitance is t ox
ilitymobility
POSD
A
C g = kox 0
is severely
is severely curtailed
typical curtailed
(see
value
= ox
(see
of Section
Section
Ref: Weste; Serra & Smith
(
2.4.1).
= C oxWL
for electrons
t ox )
2.4.1). in an nMOS tra = V=GTL(2.2)
–14
CV ox
ds L 2 ; VVGT = V gs Vt
ds
Dr. A. Sarje
 I ds = channel
I-V Characteristic
I ds =
Qchannel
L v k = C ox

( )
polysilicon
L v W
>dsVdsat
V gs If VVtds V 2 Vds VGT , the channel (2.5) is no Wlonger inverte
gate
= C ox
(Long( (Channel)
)
= C ox
) = L
W L
say it is pinched
V gs Vt Vds 2 Vds
VGT Vds 2 Vds
off. Beyond t
this point,
ox

L
(2.5) called the drain
drain voltage has no further effectn+
on current.
n+
Substitutin
• Ids = V ( GT V dsimum )
2 Vdscurrent into EQ (2.5), we find an expression for th
p-type Body

SiO2 Gate Oxide

W
• = C oxpendent
; VGT of = VV .V (insulator, ox = 3.9 0)
Where, ds (2.6)
W L gs t
• At FIGURE
pinch 2.6off, Vds=Vgs-Vt
Transistor dimensions

= C ox ; VGT = V gs Vt (2.6)
• V GT is the over drive
L voltage
m Vgs – Vt arises so often that it is convenient to • Saturation
abbreviate current it as VGTds. I = V 2
2 GT
cribes the linear region oflinear
operation, for V > Vt , but Vds relatively small. It is
• Ids
s –resistive
or
is called the
because when Vds
region current
gs
Vt arises so often that it is convenient to abbreviate it as VGT
3 << VGT , Ids increases almost linearly withCV
.
oxds,
esealthe linear region of Otherfor
operation, sources
V > (e.g.,
V , MOSIS)
but V relatively k = It is ; check the definiti
definesmall.
gs t ds
resistor. The geometry and technology-dependent parameters are some- 2
into abecause
distive when V.dsDo<<not
single factor VGT , Ids increases
confuse of• with
this use almost linearly
the same withsymbolVds,
esistor. The geometry and
atio of collector-to-base technology-dependent
current in a bipolar transistor. parameters
Some texts are[Gray01]
some-
o a single factor . parameters
hnology-dependent Do not confuse this ause
alone into of with
constant called the“k same
prime.” symbol
3
of collector-to-base current in a bipolar transistor. Some texts [Gray01]
gy-dependent parameters kalone = Cinto
ox a constant called “k prime.”
3 (2.7)
Vdsat VGT , the channelk is=noClonger inverted in the vicinity of the drain; (2.7) we
ox
hed off. Beyond this point, called the drain saturation voltage, increasing the
no, further
VPOSD
has GT the channel
effect is
onno longerSubstituting
current. inverted in Vthe
Ref: Weste; Serra & Smith ds =vicinity
Vdsat at of
thisthe drain;
point we
ofA. Sarje
Dr. max-
 2.2 Long-Channel I-V Cha

I-V Characteristic
This expression is valid for V > V and V > V . Thus, long-channel MOS transistors
gs t ds dsat
polysilicon
gate
W

Two(Long Channel)
are said to exhibit square-law behavior in saturation. tox

key figures of merit for a transistor are I and I . I (also called I ) is the
on off n+ on
L n+
dsat
ON current, Ids, when Vgs = Vds = VDD . Ioff is the OFF current when Vgs = 0
p-type Body
and Vds = VDD .
According to the long-channel model, Ioff = 0 and SiO Gate Oxide 2
(insulator, ox = 3.9 0)

I on =
2
( V DD Vt ) FIGURE 2.6 Transistor dimensions
(2.9)
Summary
EQ (2.10) summarizes the current in the three regions:

0 V gs < Vt Cutoff
I ds = (VGT )
Vds 2 Vds Vds < Vdsat Linear (2.10)
2
VGT Vds > Vdsat Saturation
2

Example 2.1
Consider
POSD an nMOS transistor in a 65 nm process with a minimum
Ref: Weste; Serra & Smith Dr. A. drawn
Sarje channel
 I-V Characteristic
(Long Channel)

POSD Ref: Weste; Serra & Smith Dr. A. Sarje

 I-V Characteristic
(Long Channel)

2.2 Long-Channel

This expression is valid for Vgs > Vt and Vds > Vdsat . Thus, long-channel MOS transistors
are said to exhibit square-law behavior in saturation.
Two key figures of merit for a transistor are Ion and Ioff . Ion (also called Idsat ) is the
ON current, Ids, when Vgs = Vds = VDD . Ioff is the OFF current when Vgs = 0 and Vds = VDD .
According to the long-channel model, Ioff = 0 and

I on =
2
(V DD Vt ) (2.9)

EQ (2.10) summarizes the current in the three regions:

0 V gs < Vt Cutoff
I ds = (VGT )
Vds 2 Vds Vds < Vdsat Linear (2.10)
2
VGT Vds > Vdsat Saturation
2

POSD Ref: Weste; Serra & Smith Example 2.1 Dr. A. Sarje
 Saturation
0
2/3 C0 MOS Capacitances
Source Gate Drain
0
2/3 C0 Cgsol Cgdol

al device and also has fring- n+ n+

2.3
is leads to additional overlap p
acitances are proportional to
l = Cgdol = 0.2 – 0.4 f F 2.1
TABLE / m.Approximation for intrinsic MOS gate capacitance
FIGURE 2.10 Overlap capacitance
ance to find the total.
Parameter Cutoff Linear Saturation
Cgb C0 0 0
C gsolW
Cgs (2.15) 0 C0/2 2/3 C0
C gdolW
Cgd 0 C0/2 0
s a single-terminalCcapacitor attached to
g = Cgs + Cgd + Cgb C0 C0 2/3 C0 C
ause the source and drain actually form
aries with the switching activity of the
ate capacitance in a 0.35
The m process
gate for the source and drain in a real device and also has fring-
overlaps
ehavior [Bailey98].
ing fields terminating on the source and drain. This leads to additional overlap
POSD Ref: Weste; Serra & Smith Dr. A. Sarje
 Channel Length
MOS Large Modulation
Signal Model (2)
K W 2 Vds
ID Vgs Vth 1
2 L VA
1 VA
ro
ID ID
Vds Vgs

MOS large signal model with Early effect

G D
• Channel length reduces due to pinch off drain voltage Vds. Figure 4.16 VA
depends on technology
K W 2 and, for a given process,
• As Vds increases the drain-body L
V gs V
2 depletion
th
r
region increases and
o effective channel
is proportional to
length reduces. channel length L.
S
• Reduction in channel length results in increase of drain current modelled by (1+ λVds).
31-Oct-06 ENEE313 Abshire Fall 2006

• λ=1/VA

POSD Dr. A. Sarje

 geometry is illustrated in Figure 2.12. The area is AS = WD. The perimeter is PS = 2W +
the width of the transistor. Typical values
2D. Of this are W
perimeter, Cgsol = the
abuts Cgdol = 0.2
channel and–the
0.4remaining
f F / m.W + 2D does not.
FIGURE 2.10 Overlap ca

MOS Capacitances
They should be added to the intrinsic gate
The total capacitance
source to findisthe total.
parasitic capacitance
C sb = AS × C jbs + PS × C jbssw (2.16)
Drain Gate Source
C gsol
where ) = C gsolW
(the capacitance
Cjbs( overlap of the junction between the body and the bottom of the
or Theory source) has units of capacitance/area and Cjbssw (the capacitance (2.15)
of the junction
C
between
gdolthe = C
body) and the
( overlap W
gdolside walls of the source) has units of capacitance/length.
W Because the depletion region thickness depends on the bias conditions, these
ulation [Nose00b]. It is important to remember parasitics
thatarethis
nonlinear.
modelThe area junction capacitance term is [Gray01]
significantly
It is convenient to view the gate capacitance as a single-terminal capacitor attached to
or Theory
ates
the gate •
the capacitance Lof transistors
Inthe
(with real D
other
operating just below threshold.
transistor
side not
FIGURE 2.12 Diffusion region geometry
Gate oxide
switching). Becauseoverlaps
the source with
and
V
C jbs = C J 1 + sb
Source
M
drain J andform
actually
(2.17)
secondMOS
Detailed Draintheregion.
terminals,
Diffusion effectiveC
Capacitance gs
gate and Cgd also
capacitance
Model variesincludes
with the switchingthe
0
overlap
activity of the
ulation [Nose00b]. ItFigure
is important tobetween
remember that gate
this model significantly
source
oned
ates
in Section
the
capacitance
and drain.
2.3.1,
capacitance of
the p–n 2.11
junction
transistors
C
Cshows
is gsol
the
operating
J
and
the the
junction
just
C
effectivegdol
source
capacitance
below
. capacitance
diffusion
at zero
threshold.
and
bias the is in
and a 0.35
highly m process for
process-dependent. MJ is the junc-
seven different
ntributes combinations
parasitic capacitance acrossofthe
tion source and region.
depletion
grading drain
coefficient, behavior [Bailey98].
Theincapacitance
typically the range of 0.5 to 0.33 depending on the abruptness of
on bothMorethe areaaccurate
AS and sidewall perimeter
modeling the PS ofgate
ofdiffusion
the the source
junction. diffusion region.
0 is themay
capacitance beThe
built-in achieved
potential that by
depends
usingon adoping levels.
charge-
Detailed
based
MOS
is illustrated •
model
Diffusion
Total
in Figure delay
2.12.
[Cheng99].
Capacitance
The capacitance
area
For
is AS = WD.
the purpose
Model is given
The perimeter
of delay
is PSby
calculation
his perimeter, W abuts the channel and the remaining W + 2D does not. = v ln NA N D
= 2W +
of digital circuits, we usually
(2.18)
oned in SectionC2.3.1,
approximate = C the+ p–n
C junction
+ C between
C + 2C theWsource
or use diffusion
an
0 effective
T and2the capacitance extracted
total source parasiticgcapacitance
gs is
gd gb 0 gol n
ntributes parasitic capacitance across the depletion region. The capacitance i

•
on both the areaJunction capacitances:
sb = sidewall
AS Cand AS × C is the
v+TPS × C thermal
jbsperimeter PS of the
jbssw
Source
voltage
source and
fromdiffusion Drain
thermodynamics,
(2.16)
region. notjunction
The to be confused(p-n
with the threshold
voltage Vt . It has a value equal to kT/q (26 mV at room temperature), where k = 1.380 ×
is illustrated injunction)
Figure 2.12. have
The
here Cjbs (the capacitance of the junction
10
areajunction
is AS the
between
–23 J/K is
= WD. capacitance.
body
Boltzmann’s
The
and perimeter
the bottom
constant, T is of PS = 2W +
is the
absolute temperature (300 K at room temperature),
his perimeter, W abuts the Case 1and the remaining
channel W + 2D does not.
urce) has units of capacitance/area and and Cqjbssw (the ×capacitance
= 1.602 –19
10 C is the of charge
the junction
of an electron. NA and ND are the doping levels of
total
tweensource parasitic
the body and thecapacitance
side walls of is
the body
source)
andhas unitsdiffusion
of capacitance/length.
•
source region. ni is the intrinsic carrier concentration in undoped
Because the depletion regionCase thickness depends
silicon
2 and has on the bias
a value × 1010
conditions,
of 1.45 –3 at 300 K.
/Cthese
Cgcm
rasitics are nonlinear. The = AS
C sbarea × C jbscapacitance
junction + PSsidewall
The × C term
0capacitance
jbssw is [Gray01]
0
(2.16)
term is of a similar form but uses different coefficients.
here Cjbs (the capacitance of the junction Mbetween0the body and1.3the bottom CaseofV1 the
M JSW
Case 3V sb J

urce) has units of capacitance/area

C jbs = C J 1 + and Cjbssw (the
0 capacitance
C jbssw =of the 1junction
C(2.17)
JSW + sb (2.19)
tween the body and the side walls of 0the source) 1has units of 1.1
capacitance/length.
Case 2SW
POSD 1.0 Case 3 Dr. A. Sarje
 Body Effect
• Bodytoeffect
Body (substrate) B connected Source S. VBS=0.

•Zero
Thebias
channel
acrosspotential is
body-substrate —> No role of substrate. Effect
of determined
substrate is by capacitive coupling
ignored.
(capacitive division) between the Body effect
• gate
Bodyand
B atsubstrate terminals.
lower potential than Source S.
The substrate acts as •a second
The channel potential
“gate” for is
the MOSFET!
determined
Strong Reverse bias: wide depletion by capacitive
region coupling
of body/source —>
• The body effect is modeled as a change in threshold voltage Vth
channel (inversion) becomes weaker —>
(capacitive VGS has between
division) to be increased.
the
Increase
Vth inVthreverse
0 2bias
f Vincrease
2 f the threshold voltage.
SB -gate and substrate terminals.
where Vth 0 is the thresholdThe
voltage for VSB acts
substrate 0,
as a second “gate” for t
• Body Effect Parameter/Body factor γ
f is the builtin voltage ~0.3V,
• The body effect is modeled as a change in
• 2qN A Si
Vth Vth 0 ~0.5 V,
is a process parameter 2 f VSB - 2 f
Cox
where
N A is the doping of the substrate, Vth 0 isisthe
and thethreshold
permittivity voltage
of for VSB
silicon 0
POSD Si Dr. A. Sarje
 MOS C-V Characteristics
• C-V characteristics is central to understanding and
developing current day metal-oxide-semiconductor junctions

• C-V characteristics is still used as a diagnostic and process

monitoring tool in commercial fabrications.

• Setup:
• Adjustable DC voltage is applied across the
gate.
• AC voltage source is added to it.
• The current and voltage are monitored using
the vector ammeter and voltmeter

POSD Ref: Muller & Kamins Dr. A. Sarje

 MOS C-V Characteristics
• VG biased in accumulation region:

• Higher the negative voltage, the capacitance can be approximated

by Cox .

• At lower (more positive voltages), the accumulation layer thickness

reduced the capacitance.

POSD Ref: Muller & Kamins Dr. A. Sarje

 MOS C-V Characteristics
• VG biased in depletion region:

• Net Capacitance is Cox and Cdep in series.

• C=

POSD Ref: Muller & Kamins Dr. A. Sarje

 MOS C-V Characteristics
• VG biased in inversion at Low Freq region (VG > VTH)

• Inversion layer starts forming. Mobile charge layer forms

under the oxide.

• Capacitance decreases to oxide cap Cox.

POSD Ref: Muller & Kamins Dr. A. Sarje

 MOS C-V Characteristics
• VG biased in inversion at High Freq region (VG > VTH)

• Depletion region increases.

• Mobile charge are unable to respond fast enough and inversion layer is not
formed.

POSD Ref: Muller & Kamins Dr. A. Sarje

 Flat Band Voltage
• Flat band conditions exist when no charge is present in the semiconductor so
that the silicon energy band is flat. (It is like the built in potential of the MOS)

• The flat band voltage is obtained when the applied gate voltage equals the
workfunction difference between the gate metal and the semiconductor.
However if there is also a fixed charge in the oxide and/or at the oxide-silicon
interface, it includes it.

• VFB=ΦM - ΦS = ΦMS

• At flat band, the charge stored on the MOS becomes zero & the fields in the
oxide and silicon become zero.

POSD Dr. A. Sarje

 Inversion (recap)

• Inversion starts when VG = VT

• At point of onset of inversion, n (carrier density [electron

for a p-substrate])= p= NA

• Silicon potential = 2 φp

• Strong inversion: VG>VT

POSD Dr. A. Sarje

 Charge in M-O-S System
ACCUMULATION DEPLETION INVERSION

POSD Ref: Muller & Kamins Dr. A. Sarje

 p-Si
Total Charge density
ACCUMULATION

EE143 F2010

p-Si

POSD Ref: Muller & Kamins; Prof NCheung Lecture notes Dr. A. Sarje
 p-Si
Total Charge density
DEPLETION

POSD Ref: Muller & Kamins; Prof NCheung Lecture notes Dr. A. Sarje
 p-Si
Total Charge density EE143 F2010

INVERSION

EE143 F2010

MOS Operation Modes (co

C) Depletion: VG > VFB

Char

M
Depletion
2 Si VSi
Layer xd
thickness
qN B

2
qN Bx d qN Bx d
VG VFB
Cox 2 s
POSD Ref: Muller & Kamins; Prof NCheung Lecture notes Dr. A. Sarje
 Charge in M-O-S System
ACCUMULATION DEPLETION INVERSION

POSD Ref: Muller & Kamins Dr. A. Sarje

 • C= dQ/dV

ng, U.C. Berkeley 16

POSD Ref: Muller & Kamins Dr. A. Sarje

 Summary for MOS System

POSD Ref: Muller & Kamins Dr. A. Sarje

POSD Ref: Muller & Kamins Dr. A. Sarje