Electronic Design Automation

SET 221
M01L03S01
Synthesis Digital Circuit

Dr. Ahmed Reda Mohamed1

1The MoE Key Laboratory of Artificial Intelligence & Bio-Circuits and Systems Laboratory (BiCASL), Department of Micro-
Nano Electronics, Shanghai Jiao Tong University, Shanghai, China.
01
Outlines
 Classification of transistors
 Enhancement MOSFET
 Ch/chs of E-MOSFET as a switch
 Synthesize of CMOS digital circuit

Dr. Ahmed Reda 02

Outlines
 Classification of transistors
 Enhancement MOSFET
 Ch/chs of E-MOSFET as a switch
 Synthesize of CMOS digital circuit

Dr. Ahmed Reda 03

Classification of transistors
Transistor
Bipolar Junction Transistor Field Effect Transistor
(BJT) [Bipolar device] (FET) [Unipolar device]

npn pnp Junction FET Metal Oxide semi-conductor FET

(JFET) (MOSFET)

Enhancement MOSFET Depletion MOSFET

(E-MOSFET) (D-MOSFET)

n-channel p-channel p-channel

n-channel
Normally “off” Normally “On”
Dr. Ahmed Reda 04
Outlines
 Classification of transistors
 Enhancement MOSFET
 Ch/chs of E-MOSFET as a switch
 Synthesize of CMOS digital circuit

Dr. Ahmed Reda 05

Enhancement MOSFET (1/5)
A- Construction
n-channel Metal or
Poly silicon G p-channel Metal or
Poly silicon G
B S D B D S

- - - - - p+ ++ +++ p+
P+ n+ n+ n+
P-substrate n-substrate
Bulk Bulk
Channel Channel
Sio2
G Sio2 G
G G

S D S D D S D S

B
B
 VD > VS  VS > VD
 Current direction from Drain to Source (IDS)  Current direction from Source to Drain (ISD=-IDS)
 IG=0  IG=0
Dr. Ahmed Reda 06
Enhancement MOSFET (2/5)
B- Relation
Inputbetween
transfer
I Vs V
curve
DS GS

IDS p-channel ISD

n-channel
IG=0 IG=0
VDS VSD
VGS VSG

IDS
OFF ON Vth,p VGS

ON OFF
VGS IDS
Vth,n
 Vth,n : Threshold voltage of n-channel  Vth,p : Threshold voltage of p-channel
 VGS ≥ Vth,n to construct the n-channel  VGS ≤ Vth,p to construct the p-channel
Dr. Ahmed Reda
Ex: Vth,n =0.5 V , Vth,p = - 0.5 V 07
Enhancement MOSFET (3/5)
C- Output Characteristic curve
Relation between IDS Vs VDS
IDS IDS
n-channel p-channel
IG=0 IG=0
VDS
VGS VDS VGS

IDS VDS = VGS - Vth,n

Cutoff
Triode Saturation VDS
VGS =2.5 V

VGS =2.0 V

VGS =1.0 V
VGS =0.5 V
Saturation Triode
Cutoff VDS
Dr. Ahmed Reda
VDS = VGS - Vth,p IDS 08
Enhancement MOSFET (4/5)
D-Related Equations
n-channel p-channel
 Cutoff  Cutoff
 VGS < Vth,n IDS=0  VGS > Vth,p IDS=0
 Triode  Triode
 VGS ≥ Vth,n & VDS < VGS - Vth,n  VGS ≤ Vth,p & VDS > VGS - Vth,np
𝟐 𝟐
𝐕𝐃𝐒 𝐕𝐃𝐒
 𝐈𝐃𝐒 = 𝐁𝐧 ( 𝐕𝐆𝐒 − 𝐕𝐭𝐡,𝐧 𝐕𝐃𝐒 − )  𝐈𝐃𝐒 = −𝐁𝐩 ( 𝐕𝐆𝐒 − 𝐕𝐭𝐡,𝐩 𝐕𝐃𝐒 − 𝟐 )
𝟐
 Saturation  Saturation
 VGS ≥ Vth,n & VDS ≥ VGS - Vth,n  VGS ≤ Vth,p & VDS ≤ VGS - Vth,p
𝐁 𝐁𝐩
 𝐈𝐃𝐒 = 𝟐𝐧 (𝐕𝐆𝐒 − 𝐕𝐭𝐡,𝐧 )𝟐  𝐈𝐃𝐒 = − (𝐕𝐆𝐒 − 𝐕𝐭𝐡,𝐩 )𝟐
𝟐

Bn =μn Cox
W
L & Bp =μp Cox
W
L 𝐁𝒏 :Gain process factor n-MOSFET L: length of transistor
Cox =
εo εr
𝛍𝐧 : Mobility of electron 𝛆𝐨 : Permittivity of free space
tox
𝐂𝐨𝐱 : Gate Oxide Capacitor/unit area 𝛆𝐫 : Relative permittivity of Sio2
W:width of transistor 𝐭 𝐨𝐱 :Thickness of Sios
Dr. Ahmed Reda 09
Enhancement MOSFET (5/5)
E- 3-D construction of transistor
tox

W
P+ n+ n+
L
P-substrate
Bulk

P+ n+ n+ W

Dr. Ahmed Reda L 10

Outlines
 Classification of transistors
 Enhancement MOSFET
 Ch/chs of E-MOSFET as a switch
 Synthesize of CMOS digital circuit

Dr. Ahmed Reda 11

Ch/chs of E-MOSFET as a switch (1/5)
n-channel
Transfer “1” Transfer “0”
VDD “1” Weak VDD “1”
Good
G G

D S VO S D VO
VDD “1” GND “0”
Digital Digital
Charging Discharging C Circuit
C Circuit
VGS ≥ Vth,n VGS ≥ Vth,n
VG-VS ≥ Vth,n VG-VS ≥ Vth,n
VG=VDD & VS=VO Initially VC=VO=0 V VG=VDD & VS=0 Initially VC=VO>0 V
VDD- VO ≥ Vth,n VDD ≥ Vth,n
VO ≤ VDD - Vth,n Condition is here Condition is always valid

 When VG=VDD, n-channel E-MOSFET is ON.  When VG=VDD, n-channel E-MOSFET is ON.
 The capacitor starts charging and VO increases till  The capacitor starts discharging and VO decreases
It reaches VDD - Vth,n till It reaches GND.
 It means that Maximum value of VO equals (VDD - Vth,n)  It means that minimum value of VO equals GND “0”
Dr. Ahmed Reda ≠ VDD 12
Ch/chs of E-MOSFET as a switch (2/5)
P-channel
Transfer “1” Transfer “0”
GND “0”
GND “0”
Good G Weak
G

S D VO D S VO
VDD “1” GND “0”
Digital Digital
Charging Discharging C Circuit
C Circuit
VGS ≤ Vth,p VGS ≤ Vth,p
VG-VS ≤ Vth,p VG-VS ≤ Vth,p
VG=GND & VS=VDD Initially VC=VO=0 V VG=GND & VS=VO Initially VC=VO>0 V
- VDD ≤ Vth,p - VO ≤ Vth,p
Condition is always valid VO ≥ -Vth,p Condition is here

 When VG=GND, p-channel E-MOSFET is ON.
 The capacitor starts charging and VO increases till
It reaches VDD
 It means that maximum value of VO equals VDD
Dr. Ahmed Reda
 When VG=GND, p-channel E-MOSFET is ON.
 The capacitor starts discharging and VO decreases
till It reaches -Vth,p = Vth,p . ≠ 𝐆𝐍𝐃
 It means that minimum value of VO equals GND “0”
13
Ch/chs of E-MOSFET as a switch (3/5)
Note:- Good Weak
n-channel EMOSFET “0” “1”
p-channel EMOSFET “1” “0”
VDD VDD p-channel
E-MOSFET
Pull-Up for
Network Pull-up network

Vin Vo NOT gate A F= 𝐀

Pull-Down
n-channel
Network E-MOSFET
for
GND Pull-down network
GND
Dr. Ahmed Reda 14
Ch/chs of E-MOSFET as a switch (4/5)
Note:- Good Weak
n-channel EMOSFET “0” “1”
p-channel EMOSFET “1” “0”
VDD VDD
Pull-Up
Network
A B
Vin Vo NAND gate
F= 𝐀𝐁
Pull-Down A
Network

GND B
Dr. Ahmed Reda GND 15
Ch/chs of E-MOSFET as a switch (5/5)
Note:- Good Weak
n-channel EMOSFET “0” “1”
p-channel EMOSFET “1” “0”
VDD
VDD
A
Pull-Up
Network
Vin Vo NOR gate B
F= 𝐀 + 𝐁
Pull-Down
Network
A B
GND
Dr. Ahmed Reda GND 16
Outlines
 Classification of transistors
 Enhancement MOSFET
 Ch/chs of E-MOSFET as a switch
 Synthesize of CMOS digital circuit

Dr. Ahmed Reda 17

Synthesize of CMOS digital circuit (1/11)
In order to synthesize or implement a CMOS digital circuit for logic functions using CMOS
transistors. You have to follow these steps.

1- Simplify the function by Boolean algebra or K-map

2- Get 𝐅 by collecting “0” as a form of sum of product (SOP)

3- Firstly, draw the pull-down network by using n-channel E-MOSFET.

3.1 Any dot term will be drawn as series connection. Ex, 𝐅 =A.B A
3.2 Any sum term will be drawn as parallel connection. Ex. 𝐅 =A+B A B

Vice versa
A
A B
4- Secondly, draw the pull-up network using p-channel E-MOSFET.
B
4.1 Parallel connection is converted into series connection.
Sum term dot term
4.2 Series connection is converted into parallel connection
Dr. Ahmed Reda 18
Synthesize of CMOS digital circuit (2/11)
Ex.1. Synthesize F= 𝐀. 𝐁 using CMOS transistors and count the total
number of transistors. VDD
Ans.
A B
Setp1: F= 𝐀. 𝐁 is simplified
Setp2: 𝐅=A.B Pull-up
Setp3: Firstly, draw the pull-down network F network
 Two transistors {A,B} in series connection A
Setp4: secondly, draw the pull-up network Series to parallel

 Two transistors {A,B} in parallel connection

B
# of transistors= 2*2=4 Pull-down
network
GND
# of transistors in the pull-down transistor

Dr. Ahmed Reda 19

Synthesize of CMOS digital circuit (3/11)
Ex.2. Synthesize F= 𝐀 . 𝐁 . 𝐂 + 𝐃 using CMOS transistors and count
the total number of transistors
Ans.
Setp1: F= 𝐀 . 𝐁 . 𝐂 + 𝐃 is simplified by K-map
𝐂𝐃 𝐂

𝐀𝐁 00 01 11 10
00 1 1 0 1
01 1 0 0 1
𝐁
11 1 0 0 1
𝐀
10 1 0 0 1

Setp2: 𝐅 = A.D + B.D +C.D = D.(A+B+C)

Dr. Ahmed Reda 20
Synthesize of CMOS digital circuit (4/11)
Ex.2. Synthesize F= 𝐀 . 𝐁 . 𝐂 + 𝐃 using CMOS transistors
VDD
and count
the total number of transistors
Ans.
A

Setp2: 𝐅 = D.(A+B+C) B
D

Setp3: Firstly, draw the pull-down network

 Three transistors {A,B,C} in parallel connection. C
 All are connected in series with transistor {D}. Pull-up
network
F
Setp4: Secondly, draw the pull-up network
 Three transistors {A,B,C} in series connection. D
 All are connected in parallel with transistor {D}.
A B C
# of transistors= 2*4=8
Pull-down
GND network
SET221, Spring 2022, Dr. Ahmed Reda 21
Synthesize of CMOS digital circuit (5/11)
In order to synthesize or implement a CMOS digital circuit for logic functions using Universal gates
(NAND, NOR and NOT).
NAND Gate NOR Gate
 The function must be in form of Sum Of Product (SOP)  The function must be in form of Product of Sum (POS)
Ex: F=AB+BC+AC Ex: F= (A+B).(B+C). (A+C)
𝐅 =𝐀𝐁 + 𝐁𝐂 + 𝐀𝐂 A G1 𝐅 =(A+B).(B+C). (A+C)
B
𝐅 = 𝐀𝐁. 𝐁𝐂. 𝐀𝐂 𝐅 =(𝐀 + 𝐁) + (𝐁 + 𝐂) + (𝐀 + 𝐂)

G1 G2 G3 B G1 G2 G3
G2 G4 F
C
A
G4 G4 G1
B
A G3
C B G2 G4 F
C
# of transistors=3 *2*2+1*3*2=18
A
G3
# NAND gate C
# of terminal/gate for pull-up and down networks
Dr. Ahmed Reda
# of transistors=3 *2*2+1*3*2=18 22
Synthesize of CMOS digital circuit (6/11)
Ex. Synthesize F= 𝐀. 𝐁 + 𝐀. 𝐁 + 𝐂 using
(a) CMOS transistors (b) Universal gates (c) Compare the used transistors
in (a) and (b) Ans.
(a) CMOS transistors
Setp1: 𝐅 = 𝐀. 𝐁 + 𝐀 . 𝐁 + 𝐂 is simplified by K-map
𝐁
𝐁𝐂
00 01 11 10
𝐀
0 1 0 1 1
𝑨 1 1 1 0 1

Setp2: 𝐅 = A.B.C+ 𝐀 . 𝐁 . 𝐂 = C. (A.B + 𝐀 . 𝐁 )

Dr. Ahmed Reda 23
Synthesize of CMOS digital circuit (7/11)
Ex. Synthesize F= 𝐀. 𝐁 + 𝐀. 𝐁 + 𝐂 using
(a) CMOS transistors (b) Universal gates (c) Compare the used transistors
in (a) and (b) Ans.
(a) CMOS transistors
Setp2: 𝐅 = C. (A.B + 𝐀 . 𝐁 )

Setp3: Firstly, draw the pull-down network

 Two transistors {A,B} in series connection
 Two transistors { A . B } in series connection. C
 {A,B} and { A . B } are connected in parallel connection.
 Transistor {C} is in series connection with {A,B} and { A . B } A 𝐀

B 𝐁

Dr. Ahmed Reda GND 24

Synthesize of CMOS digital circuit (8/11)
Ex. Synthesize F= 𝐀. 𝐁 + 𝐀. 𝐁 + 𝐂 using
(a) CMOS transistors (b) Universal gates (c) Compare the used transistors
VDD
in (a) and (b) Ans.
(a) CMOS transistors 𝐀 𝐁
C
Setp2: 𝐅 = C. (A.B + 𝐀 . 𝐁 )
A B

Setp4: Secondly, draw the pull-up network VDD VDD F

 Two transistors {A,B} in parallel connection
 Two transistors { A . B } in parallel connection. C
B 𝐁 A 𝐀
 {A,B} and { A . B } are connected in series connection.
 Transistor {C} is in parallel connection with {A,B} and { A . B } A 𝐀
GND GND
Don't Forget the invertors B 𝐁
# of transistors= 2*5+ 2*2=14
Dr. Ahmed Reda GND 25
Synthesize of CMOS digital circuit (9/11)
Ex. Synthesize F= 𝐀. 𝐁 + 𝐀. 𝐁 + 𝐂 using
(a) CMOS transistors (b) Universal gates (c) Compare the used transistors
𝐀
in (a) and (b) Ans. 𝐁
G 1

(a) Universal gates

𝐀
G2 G4 𝐅
Due to the function is in form of SOP, NAND gates are used. 𝐁

𝐅 =𝐀. 𝐁 + 𝐀 . 𝐁 + 𝐂 . 𝟏
𝐂
G3
𝐅 = 𝐀. 𝐁 . 𝐀. 𝐁. 𝐂 . 𝟏 𝟏

G1 G2 G3 𝐀 G5 𝐀

G4 𝐁 G6 𝐁

# of transistors=3*2*2+ 1*3*2+3*2=24 𝐂 G7 𝐂

Dr. Ahmed Reda 26

Synthesize of CMOS digital circuit (10/11)
Ex. Synthesize F= 𝐀. 𝐁 + 𝐀. 𝐁 + 𝐂 using
(a) CMOS transistors (b) Universal gates (c) Compare the used transistors
in (a) and (b) Ans.
(C) Compare the used transistors in (a) and (b)
CMOS transistors Universal gates
# of transistors 14 24

Synthesizing by CMOS transistors requires low number of transistors,

Thus, the consumption power is low and the consumed silicon area is small

Dr. Ahmed Reda 27

Synthesize of CMOS digital circuit (11/11)
Find the transfer function of the following circuit
VDD
VDD
Pull-up
network

F A 1 B
1 2 C 2
A E
3 E
𝐅=A.B.C+E.C
B F
F=A.B.C+E.C
Pull-down
network
F=A . E + B . E +C
C
GND
GND
Dr. Ahmed Reda 28
 Thanks!

Dr. Ahmed Reda 29