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Metal Oxide Semiconductor Field Effect Transistors

MOSFET
Murad Mirzayev
Field Effect (MOS) Transistor

Typically L = 1 to 10 m, W = 2 to 500 m, and the thickness of the oxide


layer is in the range of 0.02 to 0.1 m.

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Different types of FETs

 Metal-Semiconductor FET (MESFET)


Basic MOSFET (n-channel)
 The gate electrode is
placed on top of a very
thin insulating layer.
 There are a pair of small
n-type regions just
under the drain &
source electrodes.
 If apply a +ve voltage to
gate, will push away the
‘holes’ inside the p-type
substrate and attracts the
moveable electrons in
the n-type regions under
the source & drain
electrodes.
Basic MOSFET (n-channel)
 Increasing the +ve gate
voltage pushes the p-
type holes further away
and enlarges the
thickness of the created
channel.
 As a result increases the
amount of current which
can go from source to
drain — this is why this
kind of transistor is
called an enhancement
mode device.
 Cross-section and circuit symbol of an n-type
MOSFET.
Operation
The enhancement-type NMOS transistor with a
positive voltage applied to the gate.

An n channel is
induced at the top
of the substrate
beneath the gate.

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Triode Region

> Vt ,small vDS


vGS
applied.

the channel
conductance
is proportional
to vGS - Vt,
and is
proportional
to (vGS - Vt)
vDSS.eptember 17, 8
Saturation
Region
> Vt.
vGS

The induced
channel acquires
a tapered shape
and its
resistance
increases as vDS
is increased.
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Derivation of the iD - vDS characteristic of the
NMOS transistor.

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Increasing vDS beyond vDSsat causes the channel
pinch-off point to move slightly away from the
drain, thus reducing the effective channel length
(by L).

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Drain current iD versus vDS
Enhancement-type NMOS transistor operated with vGS > Vt.

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I-V Characteristics of MOSFET
Drain current for REALLY small VD

Z  1 2
ID   C V  V V  VD 
L n i  G T 2

D Linear operation
ID 
Z
 n Ci VG  VT VD
L
 D  VG  VT 
V

Channel Conductance:

g D  ID  ZL  nC i(VG  VT
V
D VG
)
Transconductance:

g m  ID Z
 L  n Ci D
V
G VD
ECE 663 V
In Saturation

 Channel Conductance:
g D  ID 0
V
D VG

Z 2
I D sat  nCi VG VT
2L

 Transconductance:
g m  ID  Z  nC iVG  VT
V L
G VD

ECE 663
MOSFET Output Curves

 A family of curves
representing the V-I
characteristics of
transistors.
 A plot of drain
current, ID, as a
function of drain-to-
source voltage, VDS,
for several values of
VGS.
iD - vGS characteristic for an enhancement-type NMOS transistor
in saturation (V t = 1 V and k’n(W/L) = 0.5 mA/V2).

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Effect of vDS on iD in the saturation region.

The MOSFET parameter VA is typically in the range of 30 to 200 V.

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Ideal Output Characteristics of MOSFET
Ideal Transfer Characteristics of MOSFET
Voltage-Dependent Resistor
 In the ON state, the MOSFET channel can be viewed as a
resistor.

 Since the mobile charge density within the channel


depends on the gate voltage, the channel resistance is
voltage-dependent.
Comparison: BJT vs.
 MOSFET
In a BJT, current (I ) is limited by diffusion of carriers from
C

the emitter to the collector.


 ICincreases exponentially with input voltage (VBE), because the
caVBErri/eTVr concentration gradient in the base is proportional
e
to
 In a MOSFET, current (ID) is limited by drift of carriers from
the source to the drain.
 IDincreases ~linearly with input voltage (VG), because the
carrier concentration in the channel is proportional to (VG-VTH)

In order to understand how MOSFET design parameters affect


MOSFET performance, we first need to understand how a MOS
capacitor works...
Types of MOSFET
Subthreshold Conduction
CMOS
Circuit
Cross section of a CMOS integrated circuit. Note that
the PMOS transistor is formed in a separate n-type
region, known as an n well. Another arrangement is also
possible in which an n-type body is used and the n
device is formed in a p well.
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Transistors as Switches

 We can view MOS transistors as electrically


controlled switches
 Voltage at gate controls pg =a0th from

sogu=r1ce to d
drain d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Fabrication and Layout Slide 27


CMOS
Inverter
A Y
0
VDD
1

A Y

A Y
GND
Fabrication and Layout Slide 28
CMOS
Inverter
A Y
0
VDD
1 0 OFF
A=1 Y=0

ON
A Y
GND
Fabrication and Layout Slide 29
CMOS
Inverter
A Y
0 1
VDD
1 0 ON
A=0 Y=1

OFF
A Y
GND
Fabrication and Layout Slide 30

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