Microelectronics Chapter 01 Updated

Microelectronics
Chapter 01 – MOS Transistor

Winter Term 2022/23
Prof. Dr.-Ing. Matthias Kuhl
Laboratory for Microelectronics

Department of Microsystems Engineering – IMTEK
University of Freiburg
Overview
• MOS Transistor
• 𝑖(𝑣) – Characteristics
• Second-order Effects
• Short-channel Effects
• Passive Devices & Wiring
22-10-26 Microelectronics 2
Overview
• MOS Transistor
• 𝒊(𝒗) – Characteristics
• Configuration / Biasing
• Operating Regions
• NMOS vs. PMOS
Semiconductor – Silicon – Doping

Adapt the electrical properties of silicon by doping the semiconductor with group 3 elements
(acceptors: boron – B) or group 5 elements (donors: arsenic – As).
electron
electron hole electron

boron– arsenic+
- - - - holes+ e- + + + +
- - - - + + + +
Diode
Al (contact)
- vD + +
vD iD
n+ p+
n+
p+
-
depletion region 𝑖 (𝑣 ) – characteristic
p-substrate
𝑖 =𝑖 𝑒 −1
Parasitic forward-biased diodes are very critical in MOS technology!

--> parasitic BJT, latch-up, etc.
MOS-Transistor
S G D
tFOX poly
tox metal metal
Y Y´
n+ L n+
n+ L
cross-sectional view p-substrate
S
W
D
Y Y´
top view
Bird’s View – MOS Symbol & Terminals
vSB vGS iD
B S G D
vDS
G B vDS
vGS vSB
W
S
p+ n+ L n+
exemplary values:
𝐿 = 0.12 µm
𝑊 = 0.24 µm
p-substrate
𝑡 = 2.7 nm
Process Development
supply process thickness of
voltage (minimal L) gate oxide
5V 0.5 µm 8 nm
3.3 V 0.35 µm 5.4 nm
2.5 V 0.25 µm 3.2 nm
1.8 V 0.18 µm 2.0 nm
1.2 V 0.13 µm 1.5 nm
1.0 – 1.2 V 90 nm 1.2 nm
1.0 V 65 nm 1.2 nm SiO2 replaced by new materials with
2.5 nm higher relative dielectric constant
1.0 V 45 nm (“high k” materials, e.g., ZrO2 or HfO2)
(SiO2: 1.0 nm)
in order to continue the
2.3 nm shrinking process.
1.0 V 32 nm
(SiO2: 0.9 nm) 𝜀, = 3.9 ↔ 𝜀 , = 25
Overview
• MOS Transistor
• NMOS vs. PMOS
𝑖(𝑣) - Characteristic – Subthreshold Region
B S vGS << Vth G D

D
vDG iD
G vDS
vGS
p+ n+ n+
S
+ + + + +
+ + + +
p-substrate
Depletion region is formed! subthreshold region

However, the transistor is still turned off! 𝑣 ≪𝑉 𝑉 – threshold voltage
There is no inversion layer yet!
𝑖 ≈ 0A
𝑖(𝑣) - Characteristic – Strong Inversion
B S vGS > Vth G D

D
vDG iD
G vDS
vGS
p+ n+ n+
S
+ + + + +
charge in inversion layer + + + +
(gate-channel plate capacitor) p-substrate
𝑄 = −𝐶 𝑊𝐿 𝑣 −𝑉 (strong) inversion
with 𝐶 = 𝑣 >𝑉
Inversion layer is established, current may flow.
𝑖(𝑣) - Characteristic – Strong Inversion

vDS << vGS - Vth
• charge in inversion layer
B S vGS > Vth G D
𝑄 = −𝐶 𝑊𝐿 𝑣 −𝑉
• current flows if vDS > 0 V, electrons move with
drift velocity:
𝑣⃗
𝑣⃗ = −𝜇 𝐸 = −𝜇 p+ n+ n+
𝐿
• passed travel time until total channel charge + + + + +
has reached the drain + + + +
p-substrate
𝐿 𝐿 𝐿
𝑡 = = =
𝑣⃗ 𝜇 𝑣⃗ 𝜇 𝑣
voltage responsible for
• for 𝑣 ≪, current results from −𝑄 = 𝑖 𝑡
• charge
Distinguish two operating regions: 𝑊
𝑖 =𝜇 𝐶 𝑣 −𝑉 𝑣 • current
linear and saturation! 𝐿
𝑖(𝑣) - Characteristic – Linear Region
D vDS ≤ vGS - Vth
linear region
iD
vDG B S vGS > Vth G D
𝑣 >𝑉 G vDS
vGS
𝑣 ≤𝑣 −𝑉 S
charge density in channel at point X p+ n+ n+

with infinitesimal width ∆𝑥 vGC(hannel)
∆𝑄 𝑥 = −𝐶 𝑊∆𝑥 𝑣 (𝑥) − 𝑉
vGS
vGD = vGS-vDS p-substrate
𝑣
𝑖 =𝛽 𝑣 −𝑉 − 𝑣 Vth
2 x
𝑊 𝑣 S D
= 𝛽 𝑣 −𝑉 − 𝑣
𝐿 2
with 𝛽 =𝜇 𝐶 =𝜇
Derivation will be presented in our concentration course
Analog CMOS Circuit Design.
MOS transistor in linear region = voltage-controlled resistor → 𝑓( , 𝑣 ).

𝑖(𝑣) - Characteristic – Saturation Region

D vDS ≥ vGS - Vth
saturation region
iD
𝑣 >𝑉 G vDS
vGS
𝑣 ≥𝑣 −𝑉 S
p+ n+ n+
𝑣 <𝑉 → no inversion
vGC(hannel)
𝛽 vGS
𝑖 = 𝑣 −𝑉 p-substrate
2
𝛽 𝑊 Vth
= 𝑣 with 𝛽 =𝜇 𝐶 =𝜇 vGD x
2 𝐿 S D
channel pinches off
𝑖 is no longer a function of 𝑣 ! if 𝑉 = 𝑉 − 𝑉
MOS transistor in saturation = voltage-controlled current source → 𝑓( , 𝑣 ).

𝑖(𝑣) - Characteristic – Saturation Region
D vDS ≥ vGS - Vth
saturation region
iD
𝑣 >𝑉 G vDS
vGS
𝑣 ≥𝑣 −𝑉 S
p+ n+ n+
𝑣 <𝑉 → no inversion
𝛽
𝑖 = 𝑣 −𝑉 p-substrate
2
𝛽 𝑊
= 𝑣 with 𝛽 =𝜇 𝐶 =𝜇 𝑉 𝑉 𝑉 −𝑉 𝑣
2 𝐿 𝑖
(mV) (mV) (mV) (mV)
300 200 100 >100 𝐼
400 200 200 >200 4𝐼
Ideal - Transfer Characteristic

𝑊 𝑣 𝛽 𝑊
𝑖 = 𝛽 𝑣 −𝑉 − 𝑣 𝑖 = 𝑣 −𝑉
𝐿 2 2 𝐿
iD linear region saturation region
(triode or resistive) (pinch off)
vDS  vDSsat vDS  vDSsat
VGS3
D
iD
channel pinches off
quadratic
if vDS > vGS - Vth

G vDS
vGS
VGS2
S
VGS1
vDS
Case Study – 𝑖 (𝑣 ) - Transfer Characteristic (CMOS 0.12 µm)
• 0.12 µm CMOS technology, 𝑉 = 0.19 V, 𝛽 = 370 µA/V iD

• Simulate 𝑖 versus 𝑣 of a = device for different 𝑉 !
• Compare the results with the calculation! D
G vDS varies
20uA
VGS = 0.50 V, ID = 18.0 µA (calculated)
B
S
VGS fixed
15uA
10uA VGS = 0.40 V, ID = 8.2 µA (calculated) 𝛽 𝑊

𝑖 = 𝑣 −𝑉
2 𝐿
5uA
0A
0V 0.2V 0.4V 0.6V VGS = 0.25 V,
0.8VID = 0.6 µA (calculated) 1.2V
1.0V
ID(M1)
V_UDS
Overview
• MOS Transistor
• NMOS vs. PMOS
pMOS Transistor – Strong Inversion
D G S B
Everything is inverted! vGS < Vth
p-substrate  n-substrate
p+ doping (bulk)  n+ doping
n+ doping (source, drain)  p+ doping p+ p+ n+
negative Vth
- - -- - - - - -
(strong) inversion n-substrate
𝑉 <0V
Inversion layer is established, current may flow.
𝑣 <𝑉
As for nMOS transistor, a linear and
saturation region are to be distinguished.
nMOS versus pMOS Transistor

B S G D D G S B
p+ n+ n+ p+ p+ n+
p-substrate n-substrate
D D
iD iD < 0 A linear region

B 𝑣
G vDS G vSB < 0 V 𝑖 =𝛽 𝑣 − 𝑉 𝑣 −
B 2
vGS vSB
saturation region
vGS < 0 V vDS < 0 V 𝛽
S S 𝑖 = 𝑣 − 𝑉
2
CMOS Technology – Single-Well Process
VSS S G D D G S VDD
S vBS > 0 V
vSG > 0 V
p+ n+ n+ p+ p+ n+
G
n-channel transistor p-channel transistor n-well B
iD
p-substrate
D vSD > 0 V
D
iD 𝛽
𝑖 = 𝑣 − 𝑉
G B vDS 2
vGS vSB
Use the same device equations with absolute
voltage values, e.g., |vGS|!
S
CMOS Technology – Twin-Well Process
Each transistor exhibits a separate bulk contact!
VSS VDD B S G D D G S B
p+ n+ p+ n+ n+ p+ p+ n+
n-channel transistor p-channel transistor
p-well
n-well n-well
p-substrate
Sometimes also called a “Triple-Well Process” since the p-substrate is

often realized as an epitaxial layer and thus considered as a “global well”.
Case Study – 𝑖 (𝑣 ) - Transfer Characteristic (CMOS 0.12 µm)
• 0.12 µm CMOS technology, 𝑉 = 0.21 V, 𝛽 = 65 µA/V

• Simulate 𝑖 versus 𝑣 of a = device for different 𝑉 !
VGS fixed
• Compare the results with the calculation! S
15uA
VGS = 0.50 V, ID = 13.7 µA (calculated) G
B v varies
D DS
iD
10uA VGS = 0.45 V, ID = 9.4 µA (calculated)
|iD| VGS = 0.40 V, ID = 5.9 µA (calculated) 𝛽 𝑊

𝑖 = 𝑣 − |𝑉 |
5uA
2 𝐿
0A
0V
IS(M2)
0.2V 0.4V VGS = 0.25 V, I0.8V
0.6V
D = 0.3 µA (calculated)
1.0V 1.2V
|vDS|
V_UDS
MOS-Transistor – Symbols
enhancement depletion enhancement depletion
D D
n-channel MOS G B G B
S S
S S
p-channel MOS G B G B
D D
Used in our courses!
Overview
MOS Transistor
• Effective Channel Length & Width
• Channel-length Modulation
• Body Effect
• Subthreshold Current
• Latch-up
• Capacitances
Effective Channel Length
𝑡ox
Y Y´
n+ 𝐿eff = 𝐿 n+
𝐿drawn
n+
∆𝐿 ∆𝐿
The design software determines
p-substrate
𝐿 so that 𝐿 = 𝐿.
Y S G D Y´
Effective Channel Width
𝑊 =𝑊
Y Y´
𝑊
∆𝑊 ∆𝑊
D The design software determines

𝑊 so that 𝑊 = 𝑊.
Y G Y´
S
Overview
MOS Transistor
• Body Effect
• Latch-up
• Capacitances
Channel Length Modulation
𝑣 >𝑣 −𝑉
Saturation Region B S 𝑣 >𝑉 G D
𝑣 >𝑉
𝑣 >𝑣 −𝑉
p+ n+ n+
𝐿’
𝜇𝐶 𝑊 𝐿 ∆𝐿
𝑖 = 𝑣 −𝑉
2 𝐿′
p-substrate
Replacing 𝐿’ by 𝐿 – ∆𝐿, performing a

∆ 𝛽
Taylor approximation, and assuming that = 𝜆𝑣 yields: 𝑖 = 𝑣 −𝑉 1+𝜆𝑣
2
𝑖 slightly increases with 𝑣 in saturation!
- Transfer Characteristic
𝒊𝐃 (µ𝐀)
comparison of
transfer characteristics
𝜆>0V saturation: 𝑣 > 𝑣 − 𝑉
𝛽
𝜆=0V 𝑖 = 𝑣 −𝑉 1+𝜆𝑣
2
linear: 𝑣 <𝑣
−𝑉
1
𝑖 =𝛽 𝑣 −𝑉 − 𝑣 𝑣 1+𝜆𝑣
2
𝒗𝐃𝐒
𝐃𝐒 (𝐕)
𝑖 (𝑣 ) - nMOS Transfer Characteristic –
Determination 𝜆
0.12µm CMOS (nMOS long-channel): 𝑉 = 0.19 V, 𝛽 = 370 μA/V
Simulation of a 𝑊/𝐿 = 1µm/1µm … 100µm/100µm device for 𝑉 = 0.35 V
𝛽
6.0uA 𝐼 = 𝑉 −𝑉 1 + 𝜆𝑉
2
𝛽
𝐼 = 𝑉 −𝑉 1 + 𝜆𝑉
2
4.0uA 𝐼 −𝐼
𝜆=
𝑖 𝐼 𝑉 −𝐼 𝑉
The longer the device,

2.0uA
• 10µ/10µ − 𝜆 = 0.02 V the smaller 𝜆!
• 2µ/2µ − 𝜆 = 0.10 V
Δ𝐿
𝜆∼
• 1µ/1µ − 𝜆 = 0.15 V 𝐿
0A
0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V
ID(M1)
𝑣
V_UDS
- nMOS Transfer Characteristic

𝛽
Simulation of a = 1µm/1µm device for 𝑣 = 0.25 … 0.5 V 𝑖 = 𝑣 −𝑉 1 + 𝜆𝑣
2
16uA
12uA
𝑖 Slope varies for

8uA
different 𝑖
→ 𝜆(𝑣 )
4uA
0A
0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V
ID(M1)
𝑣
V_UDS
𝑖 (𝑣 ) - nMOS Transfer Characteristic – Slope

Simulation of a 𝑊/𝐿 = 1µm/1µm … 100µm/100µm device for 𝑉 = 0.35 V
𝛽
6.0uA 𝐼 = 𝑉 −𝑉 1 + 𝜆𝑉
2
𝛽
𝐼 = 𝑉 −𝑉 1 + 𝜆𝑉
2
4.0uA
𝑖 The slope in saturation

results in
2.0uA 𝐼 −𝐼 𝛽
• 10µ/10µ − 𝜆 = 0.02 V =𝜆 𝑉 −𝑉
𝑉 −𝑉 2
• 2µ/2µ − 𝜆 = 0.10 V
• 1µ/1µ − 𝜆 = 0.15 V
0A
0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V
ID(M1)
𝑣
V_UDS
𝑖 (𝑣 ) - pMOS Transfer Characteristic
Simulation of a = 5µm/1µm device for 𝑣 = 0.25 … 0.5 V

15uA
The longer the device,
the smaller 𝜆!
Δ𝐿
𝜆∼
10uA 𝐿
𝑖
• 10µ/10µ − 𝜆 = 0.005 V
• 10µ/2µ − 𝜆 = 0.020 V
5uA
• 1µ/1µ − 𝜆 = 0.040 V
0A
0V 0.2V 0.4V 0.6V 0.8V 1.0V 1.2V
IS(M2)
𝑣
V_UDS
Overview
MOS Transistor
• Body Effect
• Latch-up
• Capacitances
Body Effect
B S G D
p+ n+ n+
Not necessarily connected!
p-substrate
The bulk (B) of an nMOS (pMOS) transistor is usually nMOS: 𝑣 ≤𝑣 ≤𝑣

connected to the lowest (highest) potential in order to keep
the SB and DB diodes reverse biased! pMOS: 𝑣 ≥𝑣 ≥𝑣
Body Effect – Equation
B S G D
p+ n+ n+
p-substrate
The threshold voltage always increases if 𝑣 ≠ 0 V!

𝑣 =𝑉 +𝛾
2Φ + 𝑣 − 2Φ

2𝜀 𝑞𝑁 𝑘𝑇 𝑁
𝛾 – body-effect coefficient 𝛾= Φ = ln
𝐶 𝑞 𝑛
- Transfer Characteristic
𝑖 𝑉 defined by the process

(extra implantation)
D depletion native enhancement

G 𝑖
𝑉 fixed and very small
B
𝑣 S
𝑣
triple-well process
𝑣 =𝑓 𝑣
𝑣 ≈𝑉 +𝛾 𝑣
Body effect!
𝑉 <0V 𝑉 ≈ 0V 𝑉 >0V 𝑣 ≥𝑉 𝑣
Overview
MOS Transistor
• Body Effect
• Latch-up
• Capacitances
Subthreshold Current
assumption: 𝑣GS < 𝑉 , 𝑣DS > 0 𝑖D = 0 A ?
𝑘𝑇 𝑊
𝑖 =𝐼 𝑒 1−𝑒 with 𝑉 = , ζ > 1, 𝐼 = 𝜇 𝐶 𝑉
𝑞 𝐿
for 𝑣DS > 200 𝑚𝑉
𝑖 ≈𝐼 𝑒
There is current flowing for 𝑣GS < 𝑉th! 𝑖
However, it is very small!

≈ 80 mV/decade
 subthreshold circuit design
𝑉
(no topic of this lecture)
𝑣
Overview
MOS Transistor
• Body Effect
• Latch-up
• Capacitances
Latch-up
𝑉 S G D S G D 𝑉𝐷𝐷 𝑉DD
thyristor
𝑅W
𝑣BE2
𝑅W
𝑣BE1
𝑅S
𝑅S
formation: requirement: 𝛽1𝛽2 > 1
voltage drop on 𝑅W 𝑉SS
protective measures:
 𝑣BE2 turns on process: * highly doped buried layer  𝑅s, 𝑅w
 voltage drop on 𝑅S * oxide trenches
 𝑣BE1 turns on  development of thyristor not feasible
 voltage drop on 𝑅W increases… circuit: * large interspace  𝛽
reason: * guard rings (= many substrate/well contacts)
peaks in 𝑉DD and/or 𝑉SS  stabilization of substrate/well potential
Overview
MOS Transistor
• Body Effect
• Latch-up
• Capacitances
MOS Transistor – A Complicated Capacitor
B S 𝑣GS > 𝑉th G D
p+ n+ n+
+ + + + +
+ + + +
p-substrate
MOS Transistor – Parasitic Capacitors
S G D
𝐶GSov 𝐶ox 𝐶GDov

n+ n+ 𝐶GBov 𝐶GBov
𝐶SB + + 𝐶D + + 𝐶DB
𝑌 – cut – 𝑌’ p-substrate 𝑋 – cut – 𝑋’ p-substrate
D
𝐿
𝐶GD 𝐶DB
S G B
G 𝑊 D
𝑌 𝑌´ 𝐶GS 𝐶SB
transistor layout
top view
𝐶GB
22-10-26 Microelectronics
S 45
Capacitances – Approximated Calculation

S G D
𝐶GSov 𝐶ox 𝐶GDov

n+ n+ 𝐶GBov 𝐶GBov
𝐶SB 𝐶D 𝐶DB
𝑌 – cut – 𝑌’ p-substrate 𝑋 – cut – 𝑋’ p-substrate
𝐶
𝐶 ≈𝐶𝐴 +𝐶 𝑃 n+
𝐿 (junction sidewall cap.)
𝐶 ≈𝐶𝐴 +𝐶 𝑃 𝐶 (junction cap.)
S G 𝑊 D 𝐶 ≈𝐶 𝑊 𝐶 ≈ 𝐶 𝑊𝐿
𝑌 𝑌´
𝐶 ≈𝐶 𝑊 𝑁
𝐶 ≈ 𝑞𝜖 𝑊𝐿
𝐶 ≈ 2𝐶 𝐿 4Φ
Our CMOS 0.13 μm Technology – Case Study
B S G D
𝜖 𝜖
𝐶 ≈ 𝐶 𝑊𝐿 = 𝑊𝐿
𝑡
𝑡 𝑊
p+ n+ n+
with 𝐿
• 𝐶 – sheet capacitance of the gate-oxide capacitor
• 𝑊, 𝐿 – width & length of the transistor p-substrate
• 𝜖 – relative dielectric constant (SiO2: 3.9)

• 𝜖 – permittivity of the free space (8.854 ∗ 10 Vs/Am or C /Nm )
• 𝑡 – thickness of the insulator (our technology: t = 2.73 nm)
𝜖 𝜖 F fF We talk of μm
𝐶 = = 0.012 = 12
𝑡 m μm in Microelectronics!
Our CMOS 0.13 μm Technology – Case Study

How to extract the sheet capacitance 𝐶 by simulation? 𝑊 100 µm
=
 Simulate the −3 dB cut-off frequency 𝑅 = 1 kΩ G 𝐿 1 µm
of an RC low-pass filter 𝑣 = 0.6 V + 𝑣
S D
B
(𝐶 implemented by 𝐶 of the transistor)
• 𝜔=
• 𝑓 = 142.7 MHz (simulated)
• 𝜔 = = 2𝜋𝑓 = 896 Mrad⁄s
• 𝐶 = 1.15 pF
• → 𝐶 = 11.5 fF⁄(μm)
𝜖 𝜖
𝐶 = = 12 fF⁄ μm
𝑡
Capacitances – Dependence on Operating Point
Subthreshold: 𝑣GS < 𝑉

• no inversion layer → no channel between source and drain
Linear region: 𝑣GS > 𝑉 and 𝑣 < 𝑣 − 𝑉

• inversion layer → continuous channel between source and drain
S G D
Saturation region: 𝑣GS > 𝑉 and 𝑣 > 𝑣 − 𝑉
• inversion layer → pinched-off channel
between source and drain 𝑪𝐆𝐒𝐨𝐯 𝑪𝐨𝐱 𝑪𝐆𝐃𝐨𝐯
• drain has “no connection” to channel n+ n+
𝑪𝐒𝐁 𝑪𝐃𝐁
𝑪𝐃
p-substrate
Capacitances – Linear Region

S G D D
𝐶GD 𝐶DB
𝑪𝐆𝐒𝐨𝐯 𝑪𝐨𝐱 𝑪𝐆𝐃𝐨𝐯
G B
n+ n+
simulation: 𝑣GS = 0.5 V, 𝑣DS = 0.05 V 𝐶GS 𝐶SB
𝑪𝐒𝐁 𝑪𝐃 𝑪𝐃𝐁
nMOS 0.13µm BSIM
p-substrate
same area 𝐶GB
S
W/L = 10/10 W/L = 1/10 W/L = 10/1 W/L = 1/1
Calc. Sim. Calc. Sim. Calc. Sim. Calc. Sim.
𝐶 1200f 1/10 120f 120f 1/10 12f
𝐶 23f 3f 2.5f 0.3f
𝐶 ≈ 0.5 ⋅ 𝐶 + 𝐶 600f 455f 60f 45f 60f 43f 6f 4.3f
≈ 1/10
𝐶 ≈ 0.5 ⋅ 𝐶 + 𝐶 600f 570f 60f 1/10 56f 60f 60f 6f 5.99f
~W~const
𝐶 (𝐿 , = 0.75µm) 5.3f 0.53f 5.3f 0.53f
≈
𝐶 (𝐿 , = 0.75µm) 5.4f 1/10 0.54f 5.4f 1/10 0.54
Capacitances – Saturation Region
S G D D
𝐶GD 𝐶DB
𝑪𝐆𝐒𝐨𝐯 𝑪𝐨𝐱 𝑪𝐆𝐃𝐨𝐯
G B
n+ n+
simulation: 𝑣GS = 0.5 V, 𝑣DS = 1.2 V 𝐶GS 𝐶SB
𝑪𝐒𝐁 𝑪𝐃 𝑪𝐃𝐁
nMOS 0.13µm BSIM
p-substrate
S 𝐶GB
W/L = 10/10 W/L = 1/10 W/L = 10/1 W/L = 1/1
Calc. Sim. Calc. Sim. Calc. Sim. Calc. Sim.
𝐶 1200f 120f 120f 12f
~W~const
𝐶 50f 5f 4.5f 0.5f
~W~const
𝐶 ≈𝐶 5f ~W~1/10 0.5f 3f 0.3f
𝐶 ≈ 60% 𝐶 + 𝐶 800f 747f 1/1080f 74f 80f 78f 1/10 8f 7.8f
𝐶 (𝐿 , = 0.75µm) 4.1f 0.41f 4.1f 0.41f
𝐶 (𝐿 , = 0.75µm) 5.4f 0.54f 5.4f 0.54f
MOS Transistor – Summary Equations

subthreshold region 𝑣 <𝑉 valid for channels with W, L>1mm
𝑖 ≈0A
linear region 𝑣 >𝑉 && 𝑣 <𝑣 −𝑉

1
𝑖 =𝛽 𝑣 −𝑉 𝑣 − 𝑣 (1 + 𝜆𝑣 )
2
saturation region 𝑣 >𝑉 𝑣 >𝑣 −𝑉

𝛽 𝑊 𝜀
𝑖 = 𝑣 −𝑉 (1 + 𝜆𝑣 ) with 𝛽 = 𝛽 =𝜇 𝐶 , 𝐶 =
2 𝐿 𝑡
𝑉 =𝑉 , +𝛾
2Φ + 𝑣 − 2Φ
Summary
MOS transistor – second-order effects

• linear region
• continuous channel between source and drain
• 𝐶 ≈ 𝐶 ≈ 𝐶 /2 (proportional to WL)
• 𝐶 & 𝐶 are minimum one order of magnitude smaller than 𝐶 & 𝐶
• saturation region
• channel pinched off at drain → “connected” only to source
• 𝐶 ≈ 0.5 … 0.75 𝐶 (proportional to WL)
• 𝐶 ≈𝐶 ≪ 𝐶 → two orders of magnitude smaller (rough estimate), proportional to W
• 𝐶 & 𝐶 are minimum one order of magnitude smaller than 𝐶
Literature
Literature
• Razavi, chapters 2.3 & 2.4, pp. 23-38
• Sedra / Smith, chapter 4.8, pp. 320-325
• Allen / Holberg, chapter 3.3, pp. 87-92
Overview
MOS Transistor
• DB- & SB-Diodes & Drain Induced Barrier Lowering (DIBL)
• Mobility Degradation
• Velocity Saturation
DB/SB Diodes & DIBL

S G D The region under the gate is not only
depleted by the gate voltage but also
partially depleted by the DB and SB
pn-junctions!
n+ n+
Effect increases with shrinking device
length!
p-substrate → 𝐿↓ → 𝑉 ↓
S G D
Effect is stronger when the transistor is
operated in saturation (large VDS)!
n+ n+  drain induced barrier lowering (DIBL)
→ 𝑣 ↑ → 𝑉 ↓
p-substrate → 𝑣 = 𝑓(𝐿, 𝑣 , 𝑣 )
Overview
MOS Transistor
Mobility Degradation – Vertical Field

E↑
S 𝑣 ≥𝑉 G D
 channel becomes “shallower”
 carrier scattering
E  mobility 𝜇 ↓
n+ n+
𝜇
empirical model: µ = 𝜃 =?
1 + 𝜃(𝑣 − 𝑉 )
p-substrate 1 𝜇 𝐶 𝑊
saturation current: 𝑖 = 𝑣 −𝑉
2 1+𝜃 𝑣 −𝑉 𝐿
Taylor-approximation for 𝜃(𝑣 − 𝑉 ) << 1

1 𝑊 higher harmonics
𝑖 ≈ 𝛽 𝑣 −𝑉 −𝜃 𝑣 −𝑉
2 𝐿 (third-order)
Overview
MOS Transistor
• Passive Devices & Interconnects
Velocity Saturation – Lateral Field

𝑣GS > 𝑉th
S G D
saturation current
𝑖 = 𝑣sat 𝑊𝐶 𝑣 − 𝑉
n+ n+
E 𝑖 linearly and not quadratically
proportional to 𝑣 − 𝑉 !
p-substrate
v 𝑖D
vsat 𝑖D~(𝑣GS − 𝑉th)2
~107cm/s
𝑔m ↓
𝑖D~(𝑣GS − 𝑉th)
𝑣⃗ = 𝜇𝐸 – long-channel equation
𝑉DSvsat < 𝑣GS − 𝑉th
~1V/µ𝑚 E 𝑣DS
- nMOS Transfer Characteristic
• All devices have the same W/L ratio.
• However, they drive different currents!
--> short-channel effects 350 mV
𝑣DS
𝑖D
• long-channel parameters: 𝑉 = 0.22 V, 𝛽 = 475 μA⁄V
• short-channel parameters: 𝑉 = 𝑥𝑥𝑥 V, 𝛽 = 𝑥𝑥𝑥 μA⁄V
𝒊𝐃 (𝛍𝐀)
𝒗𝐃𝐒 (𝐕)
Transistor Models vs. Hand Calculations

• Level 1: long-channel / “square-law” model
• easy-to-use / hand calculations
BSIM (Berkeley Short-channel IGFET Model)
• long outdated…
• efficient, highly empirical model
• Level 2: physical model
• velocity saturation & threshold variation
• > hundreds of parameters in total
• DC model requires 100 parameters
• Level 3: half empirical model
• curve fitting on measured instances • channel-length modulation
• Level 4 (BSIM): empirical model • subthreshold conduction
• became standard in 1996 • geometric dependence of electrical parameters
• very accurate in modelling short-channel effects • vertical field dependence of carrier mobility
• not that accurate in modelling the behavior in weak &
moderate inversion • carrier velocity saturation
• inappropriate for hand calculations • drain-induced barrier lowering
• EKV model: charge model • depletion charge sharing by source & drain
• not that widespread • non-uniform doping profile for ion-implanted
• very accurate in modelling the behavior of long-channel devices
MOS transistors in weak and moderate inversion
• oversimplified formulation of short-channel effects
Microelectronics – Our Teaching Approach
• hand calculations: long-channel / „square law“ model

• learn how large- & small-signal parameters scale with width, length, bias current, etc.
• results match the order of magnitude very well, yet not the absolute value
--> get absolute values & fine tune your circuits by means of simulations
• simulations: BSIM model

• very accurate
• our concentration course Analog CMOS Circuit Design (every summer term)
• learn the gm-over-ID design approach
(look-up tables of pre-simulated parameters based on the BSIM technology file)
• apply the gm-over-ID design approach to the design of circuits / hand calculations
• simulate & fine tune your design using the BSIM technology file
• result: excellent matching of hand calculations & simulations
Literature
• Razavi, chapter 16, pp. 579-600
Overview
MOS Transistor
• Resistors
• Capacitors
• Wiring & Interconnects (Vias)
Poly Resistor
polysilicon
metal
oxid
capacitor
(parasitic)
p-substrate
Diffusion Resistor
metal
oxide
n+-diffusion
reverse-biased diode
(parasitic)
p-substrate
Typically, also p+-diffusion resistor available.
Well Resistor
metal
oxide
n+ n+
n-well
(parasitic)
p-substrate
Total Resistance – Estimation
w 𝑙 𝑙 𝜌 𝑙
n+-diffusion 𝑅=𝜌 =𝜌 =
𝐴 𝑤 𝑡 𝑡 𝑤
t
+
𝜌 – specific resistance of the material
𝑙∎ = 𝑤∎ sheet/square resistance: 𝜌∎ =
(refer to process documentation)
𝑤∎
𝑙
𝑅 = 𝜌∎ = 𝜌∎ #𝑠𝑞𝑢𝑎𝑟𝑒𝑠
𝑤
Total Resistance – Estimation II
example: 0.13 µm technology
layer(s) value unit

𝑅 = 4𝜌∎ min typ max
W W
polysilicon 2.0 8.0 15.0 Ω/□
𝑅 = 0.5𝜌∎
n+-diffusion
p+-diffusion
𝑅 = 3𝜌∎
n-well
𝑅 = 𝜌∎ (0.5#𝑐𝑜𝑟𝑛𝑒𝑟𝑠 + #𝑠𝑞𝑢𝑎𝑟𝑒𝑠)
Overview
MOS Transistor
• Resistors
• Capacitors
Poly - n+ Capacitor
poly metal
n+-diffusion oxide equivalent circuit
C C
capacitor
(parasitic) p-substrate p-substrate p-substrate
Poly - Poly Capacitor
metal
poly 2
poly 1
equivalent circuit
oxide
C
capacitor capacitor
(parasitic) Cparasitic
p-substrate p-substrate
Overview
MOS Transistor
• Resistors
• Capacitors
Metal Layers – Cross-sectional View
Metal Layers – 3D View
Metal Layers – Zoom
example: 0.13 µm technology

layer(s) value unit
min typ max
metal 7 – metal 8 19.0 27.0 35.0 mΩ/□
metal 1 – metal 6 49.0 70.0 91.0 mΩ/□
via 6 – via 7 0.1 0.6 3.0 Ω/via
via 1 – via 5 0.2 1.2 4.0 Ω/via
contact 2.0 10.0 25.0 Ω/cont
Cross-sectional View of an AMD Processor
Modern CMOS Process – Cross-sectional View
metal diffusion contacts

interconnects barriers and vias
inter-level
dielectrics
retrograde
silicide source / drain gates
wells
trench gate deep buried
22-10-26 isolation oxide
Microelectronics
isolation 79

Microelectronics Chapter 01 Updated

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Microelectronics Chapter 01 Updated

Uploaded by

Copyright:

Available Formats

Microelectronics

Chapter 01 – MOS Transistor

Laboratory for Microelectronics

Semiconductor – Silicon – Doping

electron hole electron

Parasitic forward-biased diodes are very critical in MOS technology!

𝑖(𝑣) - Characteristic – Subthreshold Region

B S vGS << Vth G D

Depletion region is formed! subthreshold region

B S vGS > Vth G D

Inversion layer is established, current may flow.

𝑖(𝑣) - Characteristic – Strong Inversion

charge density in channel at point X p+ n+ n+

MOS transistor in linear region = voltage-controlled resistor → 𝑓( , 𝑣 ).

𝑖(𝑣) - Characteristic – Saturation Region

MOS transistor in saturation = voltage-controlled current source → 𝑓( , 𝑣 ).

400 200 200 >200 4𝐼

Ideal - Transfer Characteristic

if vDS > vGS - Vth

• 0.12 µm CMOS technology, 𝑉 = 0.19 V, 𝛽 = 370 µA/V iD

10uA VGS = 0.40 V, ID = 8.2 µA (calculated) 𝛽 𝑊

VGS = 0.30 V, ID = 2.3 µA (calculated)

nMOS versus pMOS Transistor

iD iD < 0 A linear region

CMOS Technology – Twin-Well Process

Each transistor exhibits a separate bulk contact!

Sometimes also called a “Triple-Well Process” since the p-substrate is

• 0.12 µm CMOS technology, 𝑉 = 0.21 V, 𝛽 = 65 µA/V

10uA VGS = 0.45 V, ID = 9.4 µA (calculated)

|iD| VGS = 0.40 V, ID = 5.9 µA (calculated) 𝛽 𝑊

VGS = 0.30 V, ID = 1.3 µA (calculated)

enhancement depletion enhancement depletion

Used in our courses!

Effective Channel Length

D The design software determines

Replacing 𝐿’ by 𝐿 – ∆𝐿, performing a

𝑖 slightly increases with 𝑣 in saturation!

The longer the device,

- nMOS Transfer Characteristic

𝑖 Slope varies for

0.12µm CMOS (nMOS long-channel): 𝑉 = 0.19 V, 𝛽 = 370 μA/V

𝑖 The slope in saturation

𝑖 (𝑣 ) - pMOS Transfer Characteristic

0.12µm CMOS (nMOS long-channel): 𝑉 = 0.21 V, 𝛽 = 65 μA/V

Simulation of a = 5µm/1µm device for 𝑣 = 0.25 … 0.5 V

The bulk (B) of an nMOS (pMOS) transistor is usually nMOS: 𝑣 ≤𝑣 ≤𝑣

The threshold voltage always increases if 𝑣 ≠ 0 V!

𝑖 𝑉 defined by the process

D depletion native enhancement

for 𝑣DS > 200 𝑚𝑉

There is current flowing for 𝑣GS < 𝑉th! 𝑖

However, it is very small!

MOS Transistor – A Complicated Capacitor

B S 𝑣GS > 𝑉th G D

𝐶GSov 𝐶ox 𝐶GDov

Capacitances – Approximated Calculation

𝐶GSov 𝐶ox 𝐶GDov

• 𝜖 – relative dielectric constant (SiO2: 3.9)

Our CMOS 0.13 μm Technology – Case Study

Subthreshold: 𝑣GS < 𝑉

Linear region: 𝑣GS > 𝑉 and 𝑣 < 𝑣 − 𝑉

Capacitances – Linear Region

MOS Transistor – Summary Equations