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MOS Transistor

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MOS Transistor
Transistor

Last presented at the MEAD course on “Advanced Analog CMOS IC Design”

EPF-Lausanne, August 26-30, 2019

MOS TRANSISTOR: MODEL AND MODES OF OPERATION

(core of the EKV compact model)
Eric A.Vittoz
Formerly at CSEM, Neuchâtel and EPFL, Lausanne, Switzerland
evittoz@ieee.org

• Introduction
• Mobile charge and drain current
• Modes of operation Important pages
• Large signal model are framed in red
• Short and narrow channel (brief) like this one
• Small-signal model
• Noise
• Mismatch
• Non-ideal effects (brief).
• MOS transistor as a pseudo-resistor.
E.Vittoz,
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MOS Transistor
Transistor

TR-1
MAIN FEATURES OF THE EKV MOS MODEL

• Based on physical parameters

- predictive
- effects of temperature included
- known sources of variability RF
- correlations between
model parameters AC DC
noise
• Hierarchical:

• Core model
- for hand (and brain) circuit analysis and synthesis
- captures main features with only 3 model parameters
- symmetrical, substrate referred (needed for analog circuits)
- provides insight in the behaviour of transistors and circuits
robust circuits.

• Continuous in wide range of currents, good at very low voltage.

E.Vittoz,
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MOS Transistor
Transistor

DEFINITIONS FOR N-CHANNEL TR-2

VD D
VG G G
ID
VS S tox S D
P+ N+ x N+ P-type local Sub
width W z L substrate
εSi ,εox permittivity of Si, SiO2 F/m
Cox = εox/tox gate oxide capacitance per unit area F/m2
Nb = constant doping concentration of substrate m-3
ni intrinsic carrier concentration m-3
pp, np concentration of holes, electrons in P-sub. m-3
UT = kT/q thermodynamic voltage V
ΦF=UTln(Nb /ni) Fermi potential of substrate V
Φms gate-substrate extraction potential difference V
V non-equilibrium "potential" in channel V
• V+ΦF = quasi-Fermi potential of electrons
• local value, withV=VS at S-end and V=VD at D-end
• will be called channel voltage
Ψ(s) (surface) potential (= 0 deep in substrate) V
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MOS Transistor
Transistor
TR-3

DEFINITIONS OF CHARGES FOR N-CHANNEL

Qg >0 Qfc constant fixed interface charge As/m2

Qi < 0 mobile inversion charge As/m2

Qb < 0 fixed depletion charge in bulk As/m2

depth z
VG Ψ=Ψs
Qg = - Qfc - Qb - Qi

-Qsi
VG- Φms- Ψs
Eox = (total charge in silicon)
tox

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 MOS Transistor
TR-4
POISSON EQUATION

d2Ψ d2Ψ d2Ψ

• Thin but long and wide channel, thus: 2
»
2
and 2
thus:
dz dx dy

• 1-dimensional Poisson equation: d2Ψ q

2 = ε (np - pp + Nb)
dz si
where: ΦF -Ψ in equilibrium Ψ-ΦF -V non equilibrium V
pp = ni e UT (no hole current) Nb = ni e UT via V and/or V
S D
Φ /U -Φ /U Φ /U
• neutrality for Ψ = V = 0 results in: Nb= ni [e F T -e F T] ≅ ni e F T

2Ψ qNb Ψ-2ΦF -V -Ψ qNb

• thus: d
2 =ε e UT - e UT + 1 = ε G (Ψ, 2ΦF +V)
dz si si
electrons holes fixed charge
Thin
qNb
• now: dΨ/dz = -Ez (vertical field), thus -dEz = ε G (Ψ, 2ΦF +V)dz
si
qNb
or, with dz = -dΨ/Ez: EzdEz = ε G (Ψ, 2ΦF +V)dΨ
si
which must be integrated from bulk (Ψ and Ez=0) to obtain Ez(Ψ, 2ΦF +V)
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 MOS Transistor
TR-5
VERTICAL FIELD Ez AND TOTAL CHARGE Qsi

Ez Ψ
2 qNb UT
∫EzdEz = Ez/2 = ε ∫
G(Ψ, V, ΦF)dΨ yields: Ez =
LD
sgn(Ψ) F(Ψ, 2ΦF +V)
0 si 0

εsiUT Ψ -(2ΦF +V) -Ψ Ψ

with: LD = and F(Ψ,V+2ΦF) = e UT -1 e UT + e UT -1 +
2qNb UT
extrinsic contribution of: electrons holes fixed
Debye length charge
F V=0 V>0
• Gauss' law: Ψ= 2ΦF
-Ezs unit area 103 V/UT
of channel 102 Ψ(s)
Δx«L 10
UT
-Ex Qsi Ex 1 weak inv, Ψ(s)
-20 20 40 60
UT
Ey=0 10-1
ΦF =14UT
Ez=0 10-2

thus: Qsi = -εsi Ezs • F represents Ez(Ψ), Ezs(Ψs) and Qsi(Ψs)

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 Transistor
MOS Transistor

VARIATION OF LOCAL SILICON CHARGE QSi TR-5b

WITH SURFACE POTENTIAL Ψs
(summary page))
contribution of: electrons holes fixed charge
QSi Ψs -(2ΦF +V) -Ψs
= e U -1 e U + e U -1 + Ψs
2qNbUTεSi T T T UT

V=0 V>0
103 Ψs= 2ΦF V/UT
102 Ψs
10
UT
1 weak inv, Ψs
-20 20 40 60
10-1
UT
ΦF =14UT
10-2

• Contribution of electrons (and holes) negligible in weak inversion

• But the current can only be carried by electrons.
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 MOS Transistor

VARIATION OF LOCAL SURFACE POT. ψs WITH GATE VOLTAGE VG TR-6

• Gauss' law including Si-SiO2 interface: εoxEox=εoxVG-Φms-ψs = -Qfc-Qsi

tox
-Qsi -Qfc
yields: VG = VFB+Ψs+ where VFB = Φms+ flatband voltage
Cox Cox

εsi UT VG-VFB Ψs εsi tox

now, since -Qsi = L F(Ψs ,2ΦF +V): = + ε L F(Ψs ,2ΦF +V)
D U T U T ox D
Ψs
UT
60 V >0
2ΦF+V
UT V /UT
40 strong inversion
2ΦF V =0
UT 20 ΦF εsi tox
=14 ; ε L =5
UT ox D VG-VFB
0 UT
0 20 40 60 80 100 120 140

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 Transistor
MOS Transistor
TR-6b

VARIATION OF LOCAL SURFACE POT. ψs WITH GATE VOLTAGE VG

(summary page)

Ψs
UT
60 V >0
2ΦF+V
UT V /UT
40 strong inversion
2ΦF V =0
UT 20
VG -VFB
0 UT
0 20 40 60 80 100 120 140

• In strong inversion:
surface potential Ψs pinned at value slightly larger than 2ΦF +V

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MOS Transistor

TR-7
LOCAL GATE CAPACITANCE
• Local gate capacitance per unit area Cg given by series connection of Cox
and Csi = -dQsi /dΨs (local capacitance of the silicon):
Cox
Cg =1+C /C
ox si Ψs-2ΦF -V -Ψs
-exp +1
εsiUT Csi εsi .exp UT UT
• Since -Qsi = F(Ψs,V+2ΦF), then C = 2C L
LD ox ox D F(Ψs,V+2ΦF)
• Combining with VG(Ψs) provides Cg (VG):
Cg /Cox
Ψs/UT
V=0
V=20UT
ΦF /UT =14 Ψs=2ΦF+V
εsi
=5 VG -VFB
CoxLD
V»2ΦF UT

• For UT « Ψs « 2ΦF+V : Csi ≅ Cd (depletion capacitance)

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 MOS Transistor

CHARGE SHEET APPROXIMATION TR-8

2ΦF+V
∞ Ψs = 20
np 108 UT
• Mobile charge: -Qi = q ∫npdz =q ∫ dΨ 30
0 E
0 z 40
4 10
50
np /Ez e 1
with N L /U =
b D T F(Ψ, 2ΦF +V)
• cannot be integrated analytically 10-4

• np/Ez ∝ ex=eΨ/mUT with 1<m<2 10-80 10 20 30 40 50 60

ex Ψ/UT
• thus 95% of Qi is at potential
Ψ > Ψs - 3 to 6UT 95%

• hence: xs x charge sheet Qi at Ψs

xs-3
• Charge sheet approximation: Qb(Ψs)
S D
• all charge Qi is at Ψ=Ψs
• depletion charge Qb controlled by Ψs:
εsi UT Ψs 2qNbεsi substrate modulation
-Qb = = ΓbCox Ψs where Γb= factor
LD UT Cox
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 MOS Transistor

TR-9
VARIATION OF MOBILE CHARGE Qi WITH SURFACE POT. Ψs

• Qi (ψs) cannot be obtained by integration of np, but we have:

• total charge in silicon: Qsi = -Cox (VG - VFB - Ψs) (from Gauss' law)
• depletion charge: Qb = -ΓbCox Ψs (charge sheet approximation)

• Thus, mobile charge: Qi = Qsi - Qb = -Cox(VG - VFB - Ψs - Γb Ψs )

-VTB
Γb 2
VTB UT =
40
dVTB dQi /Cox Γb
• Slope factor n = dΨ = dΨ = 1+ VG
s s VG 2 Ψs
4
slowly variable, thus approx. constant: -Qi
3
Cox
n Γb2/UT =
2
40 10UT
1 4

0
Ψs/UT
0 20 40 60 Ψs [UT ]
VFB
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MOS Transistor

STRONG INVERSION APPROXIMATION TR-10

• Surface potential Ψs = Ψ0 + V , where Ψ0 =2ΦF + a few UT

indep. of VG (see TR-6)
• Thus, mobile charge: Qi = -Cox[VG - (VFB + Ψ0+V + Γb Ψ0+V )]
VTB
• Threshold voltage (at equilibrium):
VG
VT0 = VTB(V=0) = VFB + Ψ0 + Γb Ψ0 -Qi
Cox
• Definition: pinch-off voltage VP = V(VTB=VG)
VT0 V
dVTB dVTB dVG VP
• Slope factor n = dΨ = dV =
s dVP thus, for fixed VG
Γb -Qi
can be evaluated at V=VP: n = 1+
2 Ψ0+VP VG-VT0 Cox
• Approximations:
VG-VT0 -Qi
VP = n ≅ n (VP-V)
Cox V
0 VP
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 MOS Transistor
TR-11
GENERAL EXPRESSION OF MOBILE CHARGE Qi (V)

Ψ-ΦF -V hence, by charge sheet Ψs-ΦF -V

electron concentr. np = ni e UT approximation Qi ∝ e UT

dQi dQi dV dQi dQi

• Thus: UT = dΨs - dV or with dΨs = : = -
Qi nCox UT nUTCox Qi

Qi
• Normalized charge: qi = - - dV = UT (2dqi + dqi /qi)
2nUTCox
(result to be used later)
• Integration yields:
strong weak inversion
const.-V = UT (2qi +lnqi ) 30
qi qi =-x/2
with const.=VP to fit with 20
• strong inversion approx. qi =e -x
-Qi /Cox = n (VP -V) » 2nUT 10

• thus weak inversion approx: 0

VP -V -60 -40 V-V -20 0 10
-Qi /Cox = 2nUT e UT « 2nUT x= U P V=VP
T
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 MOS Transistor
Transistor

VARIATION OF INVERTED MOBILE CHARGE Qi TR-12

WITH CHANNEL VOLTAGE V
(summary page)
-Qi /Cox
VT0 = threshold value of VG for V=0 (bias-independent)
VG -VT0
for constant VG
-Qi
strong inversion: = n (VP -V) linear
Cox

-Qi VP -V
weak inversion: = 2nUT exp exponential
Cox UT

for VG=VT0
0 -Qi -Qi
channel voltage V =VP - + UT ln
nCox 2nUTCox
pinch-off voltage VP

VG -VT0 Γb
with VP = n n = 1+ =1.2 to 1.6 (slowly tends to 1 for large VG)
2 Ψ0+VP
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 MOS Transistor
Transistor

DRAIN CURRENT TR-13

see TR-11
dΨ dQi dV
• With charge-sheet approxim.: ID = µW (-Qi dxs +UT ) = µW (-Qi)
dx dx
drift diffusion
• Assumption: constant electron mobility µ
• Since ID is constant along the channel, integration of the 2nd form yields:
VD - Qi /Cox
Qi VG const.
ID = β ∫ - dV with β = µCox W
Cox L strong
VS
• May be decomposed into: weak
∞ ∞ ID inversion
Qi Qi
ID = β ∫ - dV - β ∫- dV β V
Cox Cox
VS VD VS VD VP
forward current reverse current IR
(independent of VD) (independent of VS) thus: ID = IF - IR
• Forward/reverse symmetry, since IF (VS) ≡ IR (VD) (same function)
• If IR « IF, then ID = IF, transistor (forward-)saturated
• Weak inversion already possible for V=0 if VG<VT0 ("subthreshold")
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 Transistor
MOS Transistor
TR-14
MOS TRANSISTOR: MODES OF OPERATION

• For VG constant thus VP constant:

VD

IF »IR
forward
saturation

VP
VDSsat
reverse
* also called
saturation IR »IF
- conduction linear*
- triode
-VJ VP
VS
ID>0 -VJ
reverse bipolar
ID<0
VP = pinch-off voltage
equipotential channel (VD=VS, ID=0) VJ = "forward junction voltage"
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MOS Transistor
Transistor

TR-15
DRAIN CURRENT IN STRONG INVERSION

Qi βn
• - = n (VP -V), thus IF,R = (VP - VS,D)2 for VS,D < VP
Cox 2
V -V
• By using the approx. VP = G T0 this yields, for the forward mode(VD≥VS):
n
βn 2
β
Saturation: ID = IF = (VP -VS) = (VG -VT0 -nVS)2 for VD≥VP
2 2n
VDSsat
n
Linear: ID = IF - IR = β(VD -VS)[VG -VT0 - (VD+VS)] for VD≤VP
2

Blocked: ID = 0 for VS≥VP

where β = µCoxW/L

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 MOS Transistor

TR-16
FORWARD CHARACTERISTICS IN STRONG INVERSION

βn 2
(VP -VS)2 = βn VDSsat =
β (V -V - nV )2
Saturation: ID = =IF
2 2 2n G T0 S
for VD≥VP

n
Linear: ID = β (VD -VS)[VG -VT0 - 2 (VD+VS)] =IF -IR
for VD≤VP
IR
ID ID Linear Saturation

βn V 2 IF
VD 2 DSsat IR VG
βn
(VD-VS)2
2 ID = IF - IR
VG VD
VT0+nVS VT0+nVD VDSsat
VS VP
Transfer characteristics for VS=const. Output characteristics

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MOS Transistor
Transistor
TR-17
DRAIN CURRENT IN WEAK INVERSION

VP-V VP -VS,D
• -Qi /Cox = 2nUT e UT « 2nUT thus: IF,R = 2nβUT2e UT

2
• Definition: specific current of the transistor: IS = 2n βUT

• By using the approx. VP = (VG -VT0)/n , this yields:

VG -VT0 V V
- S - D
ID = IS e nUT (e UT - e UT) for IF and IR« IS
IF IR
• exponentially dependent on VT0
• therefore, the transistor must be biased by imposing ID
• Slope factor n results from capacitive divider Cox/Cd (depletion capacitance)
• it can therefore be found from the Cg(VG) curve:
Cg /Cox
• it can be evaluated at Ψs=2ΦF+VS :
1
Γb Γb
n = 1+ = 1+Cd /Cox ≅ 1+ Ψs 1/n Ψs = 2ΦF+V
2 Ψs 2 2ΦF+VS
weak inversion only 0 VG

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 MOS Transistor
Transistor
TR-18
FORWARD CHARACTERISTICS IN WEAK INVERSION

VG VS VD
- -
ID = ID0 e nUT ( e UT - e UT )
VT0
• where ID0 = IS e- nUT (saturation current for VG=VS=0)

• output (VG,VS = const.) • transfer from gate • transfer from source

(VD-VS»UT) (VD-VS»UT)
I
ID /IF saturation log D I
ID0 VS=0 VS>0 log D
1 VG ID0
5%
VD-VS VG
V
UT UT - S
0 UT
0 1 2 3 4 5 6
VD-VS VG VS
ID ∝1-e - -
UT ID ∝ e nUT ID ∝ e UT
• Barrier-controlled device; diffusion of "majority" carriers:
• channel may be much longer than diffusion length of electrons in the substrate.
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MOS Transistor
Transistor

TR-19
CONTINUOUS MODEL WEAK-STRONG INVERSION
∞ IF,R ∞
Qi -Qi
IF,R = β ∫ -
Cox
dV if,r = I = ∫ qi dV/UT where qi = 2nU C
VS,D S V T ox
S,D
qs,d qs,d
• Now: -dV = UT (2dqi + dqi /qi), hence: if,r = ∫ (2qi +1)dqi = |qi2 + qi |
0
0
(see TR-11) (where qs,d= qi at S,D)
IF,R
• Thus: if,r= = (qs,2d +qs,d ) parametric equations of
IS
VP -VS,D IF,R (VP -VS,D)
with: vs,d = = 2qs,d + lnqs,d
UT
1+4if,r -1
• Solving the first equation for qs,d yields: qs,d = 2
• which, introduced in the second equation, provides (VP -VS,D) of IF,R:
only 3 parameters:
1+4if,r -1
vp-vs,d = 1+4if,r -1 + ln 2 n, VT0 and β (or IS)

• This equation cannot be inverted to provide IF,R (VP -VS,D)

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 Transistor
MOS Transistor

TR-20

ALTERNATIVE CONTINUOUS MODEL WEAK-STRONG INVERSION

VP -VS,D
• Interpolation formula: IF,R = IS ln2 (1 + e 2UT )

• for VS,D «VP or IF,R »IS IF,R = βn (VP -VS,D)2 strong inversion
2
VP -VS,D
• for VS,D »VP or IF,R «IS IF,R = IS e U weak inversion
T

• ID = IF - IR includes all field-effect modes of operation

(but not the bipolar mode).

• Only 3 parameters: n, VT0 and β (or IS)

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MOS Transistor

COMPARISON OF CONTINUOUS MODELS TR-21

VP -VS,D IF,R
• Definitions: vp-vs,d = U if,r = I
T S

• Charge-based model (non-invertible):

vp-v = 1 + 4i +ln( 1 + 4i -1) + K curve a (v = vs,d for i = if,r)

• constant K depends on the exact definition of VT0

• K =-(1+ln2) = -1.693 with definition in strong inversion approx.
• Simple interpolation i =ln2(1+e(vp-v)/2) (alternative continuous model)
• can be inverted, which yields: b
102 i
vp-v = 2ln(e i -1) curve b
a (with K=-1.365)
1
• for K = -1.365:
• a and b coincide at i =1
10-2
• very similar elsewhere
10-4
-20 0 20 40 60 vp-v
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 Transistor
MOS Transistor

TR-22
INVERSION COEFFICIENT

• Inversion coefficient IC characterizes the mode of operation*.

• Definition: IC = the larger of IF /IS or IR /IS

• hence IF /IS in forward mode and IR /IS in reverse mode
2
• with IS = 2n βUT (10 to 1000 nA for W= L)

weak inversion: IC « 1
moderate inversion: IC around 1
⎛VDSsat ⎞ 2
strong inversion: IC = ⎝ ⎠ »1
2UT

* E. Vittoz, “Micropower Techniques”, in Design of VLSI Circuits for Telecommunication

and Signal Processing, Editors J.Franca and Y.Tsividis, Prentice Hall, 1994, page 62.
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 MOS Transistor
Transistor

CHANNEL LENGTH MODULATION TR-23

electrons (channel)
• Forward-saturated transistor: VS VP VD depletion charge
-- - -- -- -- - -- - - - -
N+ - --
N+
ΔL
P L

• Voltage drop VD -VP requires a depletion zone of length ΔL= f(VD -VP)

• Current ID in saturation therefore increases slightly with VD

• This effect can be approximated by a conductance in saturation:

gds = IF /VM (for VM»VP) ID

IF (VP)
-VM
VD
VP
• Channel-length modulation voltage VM proportional to L and approximately
independent of current (increases slowly with IC)
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MOS Transistor
Transistor
TR-24

SHORT CHANNEL EFFECTS (1)

a. Velocity saturation
• Reduction of ID and VDSsat
• Progressive effect
2µUT
• Characterized by parameter λc =
Vsat L
where Vsat is the saturation value of drift velocity

• Negligible if λc IC «1 (in strong inversion)

50 nm IC for N-channel
thus if L » 2µUT IC ≅
Vsat 20 nm IC for P-channel

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 MOS Transistor
Transistor

TR-25
SHORT CHANNEL EFFECTS (2)

VT0
b. Drain induced barrier lowering (DIBL)
long L
• First affects threshold VT0
• VT0 reduced short L
VD
• VT0 decreases with VD increasing
- increased output conductance in saturation Leff> Cox Nb
4 ε3 Φ µm fF/µm2 cm-3
si F
• abrupt effect, negligible if Leff > 15 2N 4µm 4.2 .
0.35 3.0 1015
qCox b
(dramatic at low IC if factor 5 only!)
0.18µm 0.14 15 .
1.8 1018

c. Artifact of process NB pile-up

• Example: reverse short channel (increase of VT0) !
• due to pile-up of concentration at channel ends: x
L short
L long

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MOS Transistor

TR-26

NARROW CHANNEL EFFECT

• Longer fringing field lines resulting in an increased value of VT0 :

εsi tox
ΔVT0 ≅ B ε w (ψ0 + VS) where B is a few units
ox
[Tsividis, p. 273]

• In deep submicron processes:

• shallow trench technique
• may result in a decrease of VT0 !

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 MOS Transistor
Transistor
SMALL-SIGNAL MODEL TR-27
gmsvs
-Qi VG constant
gmdvd Cox
id ID IF - IR
S D gms β= β
gmvg
vs
β gmd
gds vd gm /β β V
gs gd
vg G VS VD VP

weak strong inversion

• General: IF,R 2IF,R
• S,D transcond. gms,d βn (VP -VS,D ) = = 2βn /IF,R
UT VP -VS,D
• Gate transcond. gm (gms- gmd)/n

• In saturation IR « IF, hence ID = IF and gmd = 0 (log)

gms ID 2ID
• thus:
= ngm UT βnVDSsat=VDSsat= 2βnID
• residual SD gds ID /VM
conductance:
• intrinsic gm VM 2V M VM
voltage gain: A0=g nU = logIC
ds T nVDSsat nUT IC weak strong
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MOS Transistor

CONTINUOUS MODEL FOR TRANSCONDUCTANCE TR-28

-Qi /Cox
-QiS,D gms,d
Cox = β , thus: gms,d = - QiS,Dβ/Cox
V
VS,D
(see TR-19)
-QiS,D 1+4if,r -1 IF,R
• Now: qs,d = 2nU C = 2
where if,r = IF,R /IS =
T ox 2nβU 2 T
• thus:
gms,d y
2 weak inv.asymptote
y= =
IF,R/UT 1+ 1 +4i curve a 1.0
a
f,r strong inv.
0.8
b asymptote
• Alternative continuous model: 0.6
(math. interpolation, see TR-20)
VP -VS,D 0.4
if,r = ln2(1 + e 2UT )
0.2
• yields, by differentiation:
0 weak moderate strong inv.
gms,d 1 - e- if,r curve b 0.01 0.1 1 10 i
y= =
IF,R/UT if,r Inversion coefficient IC f,r
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MOS Transistor
Transistor

CONTINUOUS MODEL OF TRANSCONDUCTANCE TR-28b

(summary page)
IF . 2
gms= curve a
U T 1+ 1 +4IC
IF . 1 - e- IC curve b
alternative model of TR-20: gms =
UT IC
weak inv.asymptote
1.0
a
strong inv.
0.8 asymptote
b
gms 0.6
IF /UT 0.4
0.2
0 weak moderate strong inv.
0.01 0.1 1 10
Inversion coefficient IC = IF /IS

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MOS Transistor

TOTAL MOBILE CHARGE IN THE CHANNEL TR-29

L L
• Total mobile charge: QI = W ∫Qi dx = W ∫Qi dxdV
dV
0 0

dx µW(-Qi) -Qi
• Now: =
ID
and qi =
dV 2nUTCox
(see TR-13)
VD
-QI IS 2 dV
thus qI =
2nUTCoxWL
= ID ∫ i UT
q
VS
(see TR-11)
I qs I 3 q2 q
dV S 2qi + i | s
• Since: - = 2dqi + dqi /qi , then qI = I ∫ (2qi2+qi)dqi = S | 2 q
UT Dq ID 3 d
d
• introducing ID/IS = if -ir= (qs2 +qs) - (qd2 + qd) yields:
(see TR-19)

2 3 3 1 2 2 q 2 +q q +q 2 + 3q + 3q
3 (qs - q d) + 2 (qs - qd ) 2 s s d d 4 s 4 d
qI = =3
(q 2 - q 2) + (q - q ) qs + qd+ 1
s d s d
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APPROXIMATIONS OF TOTAL MOBILE CHARGE TR-30

2 3
(q - q3
) +
1 2
(q - q 2 qs2 +qsqd+qd2 + 34 qs+ 34 qd
qI = 3 s d 2 s d) = 2
(qs2 - qd2) + (qs - qd) 3 qs + qd + 1

-QI -QiS,D
with: qI = and qs,d = 2nU C
2nUTCoxWL T ox

• Strong inversion approximation: qs,d » 1

3 3 3 3
2 (QiS-Q iD ) 2 (VP -VS) -(V P - VD )
-QI =- WL 2 = WLnCox
3 (QiS -Q2iD) 3 (VP -VS)2- (VP -VD) 2

• nonlinear combination of S and D effects

• Weak inversion approximation: qs,d « 1

WL L2
-QI = - (QiS+QiD) = (IF + IR)
2 2µUT
• addition of S-controlled and D-controlled charge (diffusion)
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TR-31
SMALL-SIGNAL AC MODEL
µUT
• Quasi-static approximation: ⇒ lumped capacitors; valid for f « 2 IC+1
L
• Transadmittances: effect of
Ymk=gmk - jωCmk channel delay
• Values of capacitors
(normalized to WLCox)
weak inv. strong inversion
gds (IC«1) VD=VS
intrinsic VD>VP
transistor YmdVd C GS «1 1/2 2/3
C GD 1/2 «1
YmsVs CSB =(n-1)CGS
YmVg C DB =(n-1)CGD
(GS overlap) C GB 1-1/n (n-1)/(3n)
CovS CGS CGD 0
S G D Cm «1 0 4/15
gs Cms «1 n/6 4n/15
Cmd «1 n/6 «1
CSB CGB CDB gd
CJS CJD transcapacitors
B CovD
(S-junction) (GD overlap) (D-junction)
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TEMPERATURE EFFECTS TR-32

• Assumptions: Γb =const., VFB = const.- ΦF , with ΦF = 0.3 to 0.4 V

• Threshold voltage : VT0 ≅ VFB + 2ΦF + Γb 2ΦF = const.+ ΦF + Γb 2ΦF

dVT0 dVT0 dΦF Γb dΦF dΦF
= =(1+ ) = (2n0-1) where n0 = n (VG=VT0)
dT dΦF dT 2ΦF dT dT
VG0
NB -
Now: ΦF = UT ln with ni ≅ A.e 2UT with: A = const. and VG0 = 1.2V
ni
dVT0 n0-0.5
thus: = (2ΦF - VG0) = -1 to -2.5 mV/°C
dT T

• Transfer parameter: β = µCoxW/L

dβ/β α
with µ ∝T-α , thus: =- = -0.5 to -1%/°C
(α = 1.5 to 3) dT T

Γb dn 1 - n . dΦF
• Slope factor: n = 1 + thus =
2 2ΦF+VP dT 2ΦF +VP dT
dn n-1 .VG0 - 2ΦF
hence: dT = <0.1%/°C
2T VP + 2ΦF
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CHANNEL NOISE I TR-33

dV dx
• Resistance of an elementary length dx of channel: dR = I = Wµ(-Q )
(see TR-13, "drain current") D i

• associated noise voltage spectral density: dSV = 4kTdR [V2/Hz]

• contribution to the noise current spectral density: dSI = g2dSv
where g is the local channel transconductance :

-Qi µW dID
dID µW
β = (-Qi) ID
Cox L
g= = (-Qi)
dV L gms g gmd
V
VS V VD
dx 4kTµW V+dV
• thus: dSI = [ µW(-Qi)]2 4kT = (-Qi )dx
L W µ(-Qi ) L 2

L
4kTµ
• Total channel noise: SI = 4kTµ W ∫(-Qi) dx SI = 2 (-QI)
L2 0 L
-QI proportional to
total inverted charge QI
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MOS Transistor

CHANNEL NOISE II TR-34

By using the expressions of QI obtained in TR-30:

8 (VP -VS)3 - (VP -VD)3

• Strong inversion: SI = 3 kT nβ
(V -V )2 - (V -V )2
P S P D
• or better suited 8 1 - (1-VDS /VDSsat)3
for the direct mode: SI = kTnβVDSsat
3 1 - (1-VDS /VDSsat)2
SI
4kTgms 8
kTnβVDSsat
3
linear saturation VDS gms
1 VDSsat
• Weak inversion: or better suited
V
SI = 2q (IF + IR) for the direct mode: S = 2q I ( 1 + e- DS )
I F UT
SI
forward reverse
shot noise 2q IF =2qI =2kTgms
4kTgms
saturation VDS
4 UT
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TR-35
SILICON - OXIDE INTERFACE NOISE

• Due to trapping of carriers and mobility fluctuations

• Simplest possible modelling by an input noise voltage of spectral density:

Vm2
ρ [ As ] , process-dependent
SV = 4kT f W L

1/f flicker noise gate area

• Process-dependent parameter ρ:
Vm2
• practical range: 0.001 to 1
As
• often smaller for P-channel transistor
• slightly dependent on IC: min. around IC=1 (neglected here)
-α
• proportional to Cox , with α = 1 to 2
thus reduced with scaled down process
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MODEL OF THE NOISY TRANSISTOR TR-36

(summary page)
SI /(4kTgms) SI /(4kTgms)
D SI [A2/Hz]
1 strong inv. 1 weak inv.
G 2/3 1/2
VDS /VDSsat VDS /UT
SV [V2/Hz] 0 1 0 1 2 3
S noiseless ρ
transistor SV = 4kT (flicker noise, approximately
f WL bias-independent)
• Total equivalent noise voltage density referred to the gate input:
SI
SV + 2 ≡ 4kT RN ; defines equivalent input noise resistance RN
gm
• In saturation: gm = gms/n, thus:
n
(weak)
2gm
RN = + 2n RN gm = γ (noise excess factor)
f WL
3gm (strong)
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 MOS Transistor
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TR-37

• Resulting mismatch of:

• drain currents (same VG) • gate voltages (same ID)
δID σ gm 2 2 ID
σ σT σβ 2
σ
ID
β
ID T gm
[mV]
σT
nUT

nUT =40mV

Temp.dependent Not temp.dependent

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 MOS Transistor
Transistor

NON-IDEAL EFFECTS TR-38

• Mobility reduction at large gate voltage:

• reduction of current and transconductance (small on gm/I)
• strong inversion current no more quadratic
• Non uniform doping Nb: modifies the shape of Qi (V).

Effects due to large Nb and small tox in deep submicron processes:

• Polysilicon depletion: • VT0 increased

2
nq< n ⇒ IS = 2nq βUT
• splitting of n: VG-VT0 gms- gmd
nv >n ⇒VP = n and gm = nv
v

• Band gap widening (quantum effect): VT0 increased and IS reduced.

• Gate leakage current IG (tunnelling):

• Negligible for tox > 3-4 nm
• 10-fold increase for each 0.2nm reduction of tox

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MOS Transistor
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DEFINITION OF CURRENTS AND VOLTAGES TR-39

V+ rail
Vsub2
N-type local substrate
S
VS2
VG2 2
• Results in same equations
G2
for P- and N-channel
P-ch. T2 VD2
ID2
D2 VB • Local subtrate
• is the general substrate
D1 P for N-well process (Vsub1 = 0)
N-ch. T1 ID1 N for P-well process (Vsub2 = 0)
VD1
G1 • is not shown explicitely if Vsubi = 0
VG1
S1 V
S1
P-type local substrate
Vsub1
V- rail
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Transistor

MOS TRANSISTOR OPERATED AS A PSEUDO-RESISTOR TR-40

• From the transistor model : ISD =±(IF - IR) = ±IS [ f (VG , VS) - f (VG ,VD)]
+ is for p-channel, - for n-channel
±Qi β
• Assumption: VG=constant VG = constant
Cox IS
strong inversion
• Definition: Pseudo-voltage V* = ±V0 f(VG ,V) f(VG ,VD)
where V0 is an arbitrary positive scaling voltage weak
f(VG,VS) inversion
then, ISD (VS ,VD) may be expressed as a V
VS VD
• Pseudo Ohm's law ISD =G* (VS* -VD* ) with...
• Pseudo-conductance G*=1/R* = IS/V0 ∝ W/L; thus...

• Any network of MOS transistors connected by S and D with same VG

is linear for currents and can replace its resistive prototype

• Pseudo-ground (0-ref. for V*) obtained for f(VG ,V) negligible

(this side of the transistor saturated)
• Precision is degraded by short-channel effects.
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MOS Transistor
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EXAMPLE OF PSEUDO-RESISTORS TR-41

pseudo-ground Resistive prototype

ground
I1 I2 I1 I2
T1 T2
V1 V2 R1 R2

T3
Ia Ib R3
VG
Ia Ib
substrate
• If V1 and V2 ≥VP=(VG-VT0)/n then V1≠V2 possible (pseudo-ground).
• Otherwise V1=V2 needed.
G1(G2+G3) G1G3
• Gives: I1= Ia + Ib
G1G2+G2G3+G3G1 G1G2+G2G3+G3G1

• Where Gi=1/Ri ∝ βi and ISi

• Result is independent of the mode of operation.
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MOS Transistor
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TR-42
PSEUDO-RESISTORS IN WEAK INVERSION
• If f(VG,V) « 1 at both ends of channel weak inversion
VG-VT0
• Then: f(VG,V) = exp nU exp -V separable in VG and V
T UT
• New definitions:
-V
• pseudo-voltage V* = ±V0 exp U indpendent of V
T G
IS VG - VT0
• pseudo-conductance G* = V exp nU controllable by VG
0 T
• G* controllable by VG separately for each pseudo-resistor
• Range of current: 103 to 106 for...range of voltage: 7 to 14UT only.
• Control of G* by a current:
n-type local substrate (p-ch. transistors)
reference Vref VA TC ≡ T
(common) VB
TC IC
*=
T ⇒ G* = 1/R* = GC
*
Vref
control current IC
0*

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MOS Transistor

REFERENCES
General:
Y. Tsividis, “Operation and Modeling of the MOS Transistor”, ISBN 0-07-065523-5, McGraw-Hill, 1999.
C. Enz, F.Krummenacher and E.Vittoz, "An analytical MOS transistor model valid in all regions of operation and
dedicated to low-voltage and low-current applications", Analog Integrated Circuits and Signal Processing, Vol.8,
pp.83-114, 1995.
C. Enz and E. Vittoz, "Charge-Based MOS Transistor Modeling, The EKV Model for Low-Power and RF IC
Design", ISBN 13 978-0-470-85541-6, John Wiley & Sons Ltd, Chichester, 2006.
E. Vittoz and C. Enz, "EKV Model of the MOS Transistor", in "Sub-threshold Voltage Circuit Design for Ultra Low
Power Systems" , edit. A. Wang, B. Highsmith and A. Chandrakasan, Springer, 2006.
MOS Model for CAD: see http://ekv.epfl.ch/

Weak inversion:
E. Vittoz and J. Fellrath, "CMOS analog integrated circuits based on weak inversion operation", IEEE J. Solid-
State Circuits, vol. SC-12, pp. 224-231, June 1977.
E. Vittoz, "Micropower Techniques", in Design of VLSI Circuits for Telecommunication and Signal Processing,
Editors J.Franca and Y.Tsividis, Prentice Hall, 1994.
C. Enz and E. Vittoz, "CMOS low-power analog circuit design", in Emerging Technologies, Ch. 1.2, edited by
R.Cavin and W.Liu, The Institute of Electrical and Electronics Engineers, 1996.

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 MOS Transistor

Pseudo-resistors
K.Bult and G.J.G.M. Geelen,“An inherently linear and compact MOST-only current division technique” IEEE J. Solid-State Circuits, vol. 27,
pp. 1730-1735, December 1992.
E.Vittoz and X.Arreguit,“Linear networks based on transistors”, Electronics Letters, vol.29, pp.297-299, 4th Febr. 1993.

E.Vittoz, “Pseudo-resistive networks and their applications to analog collective computation”, Proc. MicroNeuro’97, Dresden,
pp.163-173.
E. Vittoz, C. Enz and F. Krummenacher, ”A basic property of MOS transistors and
its circuit implications”, Workshop on Compact Modelling, Nanotech 2003, WCM-MSM
2003, San Francisco, Febr. 23-27, Proc. Vol.2 pp.246-249 .
E. Vittoz, “Analog Circuits in Weak Inversion”, in “Sub-threshold Voltage Circuit Design for Ultra Low Power Systems” , edit. A.
Wang, B. Highsmith and A.Chandrakasan, Springer, 2000. Chandrakasan, Springer, 2006.
E. Vittoz, “Current-Mode Analog Circuits in Weak Inversion”, Panel EP01-06, ISSCC 2013.
E. Vittoz, “Weak Inversion Current-Mode Circuits Based on Pseudoresistors”, Solid-State Circuits Magazine, No 3, Vol.5, Summer
2013, p. 53.

TR-19: M.-A. Maher and C. Mead,“A physical charge-controlled model for the MOS transistors”, Advanced Research in VLSI, Proc. of the 1987
Stanford Conference, Ed. P.Losleben, MIT Press, Cambridge MA, 1987.
A. I. A. Cunha et al.,“An explicit physical model for long-channel MOS transistor including small-signal parameters”, Solid-State
Electronics, vol. 38, pp.1945-1952, 1995.

TR-20 H. Oguey and S. Cserveny, “MOS modelling at low current density”, Summer course on Process and Device Modelling, KU-Leuven, 1983.

TR28b: F. Silveira et al, “A gm/ID based methodology for the design of CMOS analog circuits and its application to the synthesis of a silicon-on-
insulator micropower OTA”, IEEE J. Solid-State Circuits, vol. SC-31, pp. 657-665, Sep. 1996.

P.G.A.Jespers, “The gm/ID Methodology, a Sizing Tool for Low-Voltage Analog CMOS”“, Springer 2010, ISBN 978-0-387-47101-3.

TR-37: E. Vittoz, “The design of high-performance analog circuits on digital CMOS chips”, IEEE J. Solid-State Circuits, vol. 31, pp. 657-665, June
1985.

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