Lec 7

6.
976
High Speed Communication Circuits and Systems
Lecture 7
Noise Modeling in Amplifiers
Michael Perrott
Massachusetts Institute of Technology
Copyright © 2003 by Michael H. Perrott

Notation for Mean, Variance, and Correlation
Consider random variables x and y with probability

density functions fx(x) and fy(y) and joint probability
function fxy(x,y)
- Expected value (mean) of x is
Note: we will often abuse notation and denote

as a random variable (i.e., noise) rather than its mean
- The variance of x (assuming it has zero mean) is
- A useful statistic is
If the above is zero, x and y are said to be uncorrelated

M.H. Perrott MIT OCW
Relationship Between Variance and Spectral Density
Two-Sided Spectrum One-Sided Spectrum
Sx(f) Sx(f)
A 2A
f f
-f2 -f1 0 f1 f2 0 f1 f2
Two-sided spectrum
- Since spectrum is symmetric

One-sided spectrum defined over positive frequencies
- Magnitude defined as twice that of its corresponding
two-sided spectrum
In the next few lectures, we assume a one-sided
M.H. Perrott
spectrum for all noise analysis MIT OCW
The Impact of Filtering on Spectral Density
Sx(f) |H(f)|2 Sy(f)

A B AB
f f f
0 0 0
x(t) y(t)
H(f)
For the random signal passing through a linear,

time-invariant system with transfer function H(f)
- We see that if x(t) is amplified by gain A, we have

Noise in Resistors
Can be described in terms of either voltage or current
R
R in
en
k is Boltzmann’s constant
T is temperature (in Kelvins)

- Usually assume room temperature of 27 degrees Celsius
Noise In Inductors and Capacitors
Ideal capacitors and inductors have no noise!
C L
In practice, however, they will have parasitic resistance

- Induces noise
- Parameterized by adding resistances in parallel/series
with inductor/capacitor
Include parasitic resistor noise sources

Noise in CMOS Transistors (Assumed in Saturation)
ID Transistor Noise Sources

D
G
Drain Noise (Thermal and 1/f)
S Gate Noise (Induced and Routing Parasitic)
Modeling of noise in transistors must include several noise

sources
- Drain noise
Thermal and 1/f – influenced by transistor size and bias
- Gate noise
Induced from channel – influenced by transistor size and bias
Caused by routing resistance to gate (including resistance of
polysilicon gate)
Can be made negligible with proper layout such as fingering of
devices

Drain Noise – Thermal (Assume Device in Saturation)
ind
VGS G
VD>∆V
S D
Thermally agitated carriers in the

channel cause a randomly varying 2
ind
current ∆f
- γ is called excess noise factor

4kTγgdo
= 2/3 in long channel
= 2 to 3 (or higher!) in short f
channel NMOS (less in PMOS)
- gdo will be discussed shortly
Drain Noise – 1/f (Assume Device in Saturation)
ind
VGS G
VD>∆V
S D
Traps at channel/oxide interface

randomly capture/release carriers 2
ind
∆f
drain
- Parameterized by Kf and n 4kTγgdo

1/f noise
drain thermal noise
Provided by fab (note n ≈ 1)

f
Currently: Kf of PMOS << Kf of 1/f noise
corner frequency
NMOS due to buried channel
- To minimize: want large area (high WL)
Induced Gate Noise (Assume Device in Saturation)
ing
indg
VGS G
VD>∆V
S D
Fluctuating channel potential

couples capacitively into the gate 2
ing
terminal, causing a noise gate ∆f
current
slope =
20 dB/decade
4kTδgdo
- δ is gate noise coefficient 5 ft

f
Typically assumed to be 2γ α
- Correlated to drain noise!

Useful References on MOSFET Noise
Thermal Noise
- B. Wang et. al., “MOSFET Thermal Noise Modeling for
Analog Integrated Circuits”, JSSC, July 1994
Gate Noise
- Jung-Suk Goo, “High Frequency Noise in CMOS Low
Noise Amplifiers”, PhD Thesis, Stanford University,
August 2001
http://www-tcad.stanford.edu/tcad/pubs/theses/goo.pdf
- Jung-Suk Goo et. al., “The Equivalence of van der Ziel and
BSIM4 Models in Modeling the Induced Gate Noise of
MOSFETS”, IEDM 2000, 35.2.1-35.2.4
- Todd Sepke, “Investigation of Noise Sources in Scaled
CMOS Field-Effect Transistors”, MS Thesis, MIT, June 2002
http://www-mtl.mit.edu/research/sodini/sodinitheses.html

Drain-Source Conductance: gdo
gdo is defined as channel resistance with Vds=0

- Transistor in triode, so that
- Equals g m for long channel devices

Key parameters for 0.18µ NMOS devices

Plot of gm and gdο versus Vgs for 0.18µ NMOS Device
Transconductances gm and gdo versus Gate Voltage Vgs
4
Id 3.5
Transconductance (milliAmps/Volts)
Vgs 3
M1
gd0=µnCoxW/L(Vgs-VT)
2.5
W 1.8µ
=
L 0.18µ 2
1.5
gm (simulated in Hspice)
1
0.5
0
0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
Gate Voltage Vgs (Volts)
For Vgs bias voltages around 1.2 V:

Plot of gm and gdο versus Idens for 0.18µ NMOS Device
Transconductances g m and g do versus Current Density
4
Id 3.5
Transconductance (milliAmps/Volts)
Vgs 3
M1
2.5
W 1.8µ gd0=µnCoxW/L(Vgs-VT)
=
L 0.18µ 2
1.5
gm (simulated in Hspice)
1
0.5
0
0 100 200 300 400 500 600 700
Current Density (microAmps/micron)

Noise Sources in a CMOS Amplifier
RD
enD
enG engpar
RG Rgpar
Cgd Cdb
1 vgs ro ind
ing Cgs gmvgs -gmbvs
gg
ID RD
Vout
RG
Csb endeg
vs
Vin Rdeg
RS

Remove Model Components for Simplicity
RD
enD
enG engpar
RG Rgpar
Cgd Cdb
1 vgs ro ind
ing Cgs gmvgs -gmbvs
gg
ID RD
Vout
RG
Csb endeg
vs
Vin Rdeg
RS

Key Noise Sources for Noise Analysis
RD
enD
enG
RG
ing vgs Cgs gmvgs ind

ID RD
Vout
RG
endeg
vs
Vin Rdeg
RS
Transistor gate noise Transistor drain noise
Thermal noise 1/f noise

Apply Thevenin Techniques to Simplify Noise Analysis
iout
D
G
Zg Zgs ing vgs Cgs gmvgs ind
S
iout
Zdeg D
G
Zg Zgs vgs Cgs gmvgs indg
S
Zdeg
Assumption: noise independent of load resistor on drain

Calculation of Equivalent Output Noise for Each Case
iout
D
G
Zg Zgs ing vgs Cgs gmvgs ind
S
iout
Zdeg D
G
S
Zdeg

Calculation of Zgs
iout
D
G
itest
Zg Zgs vtest vgs Cgs gmvgs
S
v1 Z
deg
Write KCL equations
After much algebra:

Calculation of η
iout
D
G
Zg Zgs vgs Cgs gmvgs itest
S
v1 Zdeg
Determine Vgs to find iout in terms of itest
After much algebra:

Calculation of Output Current Noise Variance (Power)
iout
D
Iout
G
D
G
S
Zg
Zdeg
S
Zdeg
To find noise variance:

Variance (i.e., Power) Calc. for Output Current Noise
Noise variance calculation
Define correlation coefficient c between ing and ind

Parameterized Expression for Output Noise Variance
Key equation from last slide
Solve for noise ratio
Define parameters Zgsw and χd

Small Signal Model for Noise Calculations
iout
D
Iout
G
D
G
S
Zg
Zdeg
S
Zdeg

Example: Output Current Noise with Zs = Rs, Zdeg = 0
Source
iout
ens
Rs
Vin Zgs vgs Cgs gmvgs indg
Step 1: Determine key noise parameters

- For 0.18µ CMOS, we will assume the following
Step 2: calculate η and Zgsw

Calculation of Output Current Noise (continued)
Step 3: Plug values into the previously derived expression
Drain Noise Multiplying Factor
- For w << 1/(R C

s gs):
Gate noise contribution

- For w >> 1/(R C
s gs):

Plot of Drain Noise Multiplying Factor (0.18µ NMOS)
Drain Noise Multiplying Factor Versus Frequency for 0.18 µ NMOS Device
1
f << 1/(2πRsCgs)
0.95
Drain Noise Gain Factor
0.9
0.85
0.8
f >> 1/(2πRsCgs)
0.75
1/100 1/10 1 10 100
Normalized Frequency --- f/(2πRsCgs) (Hz)
Conclusion: gate noise has little effect on common

source amp when source impedance is purely resistive!
Broadband Amplifier Design Considerations for Noise
2
indg
∆f
drain gate noise contribution
1/f noise with purely resistive
source impedance
drain thermal noise
4kTγgdo
f
1/f noise 1
corner frequency 2πRsCgs
Drain thermal noise is the chief issue of concern

when designing amplifiers with > 1 GHz bandwidth
- 1/f noise corner is usually less than 1 MHz
- Gate noise contribution only has influence at high
frequencies (such noise will likely be filtered out)
Noise performance specification is usually given in
terms of input referred voltage noise
Narrowband Amplifier Noise Requirements
2
indg
∆f
drain gate noise contribution
1/f noise with purely resistive
source impedance
drain thermal noise
4kTγgdo
f
1/f noise Narrowband 1
corner frequency amplifier 2πRsCgs
frequency range
Here we focus on a narrowband of operation

- Don’t care about noise outside that band since it will be
filtered out
Gate noise is a significant issue here
- Using reactive elements in the source dramatically
impacts the influence of gate noise
Specification usually given in terms of Noise Figure
The Impact of Gate Noise with Zs = Rs+sLg
Source
iout
Rs ens Lg
Step 1: Determine key noise parameters

- For 0.18µ CMOS, again assume the following
Step 2: Note that η =1 , calculate Zgsw

Evaluate Zgsw At Resonance
Source
iout
Rs ens Lg
Set Lg such that it resonates with Cgs at the center

frequency (wo) of the narrow band of interest
Calculate Zgsw at frequency wo

The Impact of Gate Noise with Zs = Rs+sLg (Cont.)
Key noise expression derived earlier
Substitute in for Zgsw
Gate noise contribution is a function of Q!

- Rises monotonically with Q
At What Value of Q Does Gate Noise Exceed Drain Noise?
Narrowband
2 amplifier
indg
frequency range
∆f
4kTγgdo drain thermal noise

gate noise contribution Q2
f
wo/2π
Determine crossover point for Q value
=1
- Critical Q value for crossover is primarily set by process

Calculation of the Signal Spectrum at the Output
Source
iout
Rs ens Lg
First calculate relationship between vin and iout
At resonance:
Spectral density of signal at output at resonant frequency

Impact of Q on SNR (Ignoring Rs Noise)
Narrowband
2 amplifier
indg
frequency range
∆f
signal spectrum Q2
4kTγgdo drain thermal noise

gate noise contribution Q2
f
wo/2π
SNR (assume constant spectra, ignore noise from Rs):
For small Q such that gate noise < drain noise

- SNR out improves dramatically as Q is increased
For large Q such that gate noise > drain noise
- SNR out improves very little as Q is increased
Noise Factor and Noise Figure
Equivalent output
referred current noise
enRs (assumed to be independent
Rs of Zout and ZL)
Linear,Time Invariant
vin vx Circuit inout iout
Zin (Noiseless) Zout ZL
Definitions
Calculation of SNRin and SNRout

Calculate Noise Factor (Part 1)
Source
iout
Rs ens Lg
First calculate SNRout (must include Rs noise for this)

-R s noise calculation (same as for Vin)
- SNR out:
Then calculate SNRin:

Noise Factor calculation:
From previous analysis

Modify denominator using expressions for Q and wt
Resulting expression for noise factor:
Noise Factor scaling coefficient
- Noise factor primarily depends on Q, w /w , and process specs

o t
Minimum Noise Factor
We see that the noise factor will be minimized for

some value of Q
- Could solve analytically by differentiating with respect
to Q and solving for peak value (i.e. where deriv. = 0)
In Tom Lee’s book (pp 272-277), the minimum noise
factor for the MOS common source amplifier (i.e. no
degeneration) is found to be:

How do these compare?
Plot of Minimum Noise Factor and Noise Factor Vs. Q
Noise Factor Scaling Coefficient Versus Q for 0.18 µ NMOS Device

8
7 Achievable values as
a function of Q under
Noise Factor Scaling Coefficient
6 the constraint that

c = -j0 1
= wo
5 c = -j0.55 LgCgs
c = -j1
4 c = -j0
c = -j0.55
3
Note: curves Minimum across

2 all values of Q and
meet if we
approximate 1
1 Q2+1 Q2 LgCgs c = -j1
0
1 2 3 4 5 6 7 8 9 10
Q
Achieving Minimum Noise Factor
For common source amplifier without degeneration

- Minimum noise factor can only be achieved at
resonance if gate noise is uncorrelated to drain noise
(i.e., if c = 0) – we’ll see this next lecture
- We typically must operate slightly away from resonance
in practice to achieve minimum noise factor since c will
be nonzero
How do we determine the optimum source impedance
to minimize noise figure in classical analysis?
- Next lecture!

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6.

Copyright © 2003 by Michael H. Perrott

 Consider random variables x and y with probability

 Note: we will often abuse notation and denote

 If the above is zero, x and y are said to be uncorrelated

- Since spectrum is symmetric

Sx(f) |H(f)|2 Sy(f)

 For the random signal passing through a linear,

- We see that if x(t) is amplified by gain A, we have

M.H. Perrott MIT OCW

 Can be described in terms of either voltage or current

 T is temperature (in Kelvins)

 Ideal capacitors and inductors have no noise!

 In practice, however, they will have parasitic resistance

M.H. Perrott MIT OCW

ID Transistor Noise Sources

 Modeling of noise in transistors must include several noise

M.H. Perrott MIT OCW

 Thermally agitated carriers in the

- γ is called excess noise factor

 Traps at channel/oxide interface

- Parameterized by Kf and n 4kTγgdo

 Provided by fab (note n ≈ 1)

 Fluctuating channel potential

- δ is gate noise coefficient 5 ft

- Correlated to drain noise!

M.H. Perrott MIT OCW

 gdo is defined as channel resistance with Vds=0

- Equals g m for long channel devices

M.H. Perrott MIT OCW

 For Vgs bias voltages around 1.2 V:

M.H. Perrott MIT OCW

M.H. Perrott MIT OCW

M.H. Perrott MIT OCW

ing vgs Cgs gmvgs ind

 Transistor gate noise  Transistor drain noise

Thermal noise 1/f noise

Zg Zgs ing vgs Cgs gmvgs ind

Zg Zgs vgs Cgs gmvgs indg

 Assumption: noise independent of load resistor on drain

Zg Zgs ing vgs Cgs gmvgs ind

Zg Zgs vgs Cgs gmvgs indg

M.H. Perrott MIT OCW

 Write KCL equations

 After much algebra:

M.H. Perrott MIT OCW

Zg Zgs vgs Cgs gmvgs itest

 Determine Vgs to find iout in terms of itest

 After much algebra:

M.H. Perrott MIT OCW

 To find noise variance:

M.H. Perrott MIT OCW

 Noise variance calculation

 Define correlation coefficient c between ing and ind

M.H. Perrott MIT OCW

 Key equation from last slide

 Solve for noise ratio

 Define parameters Zgsw and χd

M.H. Perrott MIT OCW

M.H. Perrott MIT OCW

Vin Zgs vgs Cgs gmvgs indg

 Step 1: Determine key noise parameters

 Step 2: calculate η and Zgsw

Consider random variables x and y with probability

Note: we will often abuse notation and denote

If the above is zero, x and y are said to be uncorrelated

For the random signal passing through a linear,

Can be described in terms of either voltage or current

T is temperature (in Kelvins)

Ideal capacitors and inductors have no noise!

In practice, however, they will have parasitic resistance

Modeling of noise in transistors must include several noise

Thermally agitated carriers in the

Traps at channel/oxide interface

Provided by fab (note n ≈ 1)

Fluctuating channel potential

gdo is defined as channel resistance with Vds=0

For Vgs bias voltages around 1.2 V:

Transistor gate noise Transistor drain noise

Assumption: noise independent of load resistor on drain

Write KCL equations

After much algebra:

Determine Vgs to find iout in terms of itest

After much algebra:

To find noise variance:

Noise variance calculation

Define correlation coefficient c between ing and ind

Key equation from last slide

Solve for noise ratio

Define parameters Zgsw and χd

Step 1: Determine key noise parameters

Step 2: calculate η and Zgsw

Step 3: Plug values into the previously derived expression

Conclusion: gate noise has little effect on common

Drain thermal noise is the chief issue of concern

Here we focus on a narrowband of operation

Step 1: Determine key noise parameters

Step 2: Note that η =1 , calculate Zgsw

Set Lg such that it resonates with Cgs at the center

Calculate Zgsw at frequency wo

Key noise expression derived earlier

Substitute in for Zgsw

Gate noise contribution is a function of Q!

Determine crossover point for Q value

First calculate relationship between vin and iout

Spectral density of signal at output at resonant frequency

SNR (assume constant spectra, ignore noise from Rs):

For small Q such that gate noise < drain noise

Calculation of SNRin and SNRout

First calculate SNRout (must include Rs noise for this)

Then calculate SNRin:

Noise Factor calculation:

From previous analysis

Modify denominator using expressions for Q and wt

Resulting expression for noise factor:

We see that the noise factor will be minimized for

For common source amplifier without degeneration