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K.Moorthi AP/ECE
Silicon Lattice
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four neighbors
Si Si Si
Si Si Si
Si Si Si
K.Moorthi AP/ECE
Dopants
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts poorly
• Adding dopants increases the conductivity
• Group V: extra electron (n-type)
• Group III: missing electron, called hole (p-type)
Si Si Si Si Si Si
- +
+ -
Si As Si Si B Si
Si Si Si Si Si Si
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P-N JUNCTIONS
• A junction between p-type and n-type semiconductor
forms a diode.
• Current flows only in one direction
p-type n-type
anode cathode
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NMOS-Transistor
Source Gate Drain
Polysilicon
SiO 2
G
n+ n+
S D
p bulk Si
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PMOS-Transistor
p+ p+
n bulk Si
K.Moorthi AP/ECE
Transistors as Switches
• We can view MOS transistors as electrically controlled
switches
• Voltage at gate controls path from source to drain
g=0 g=1
d d d
nMOS g OFF
ON
s s s
d d d
pMOS g OFF
ON
s s s
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MOS Transistor Theory
INTRODUCTION
Three modes
1. Accumulation mode
2. Depletion region
3. Inversion region
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NMOS CUTOFF
• No channel
• Ids = 0 Vgs = 0 Vgd
+ g +
• This mode of - -
s d
Operation is
n+ n+
called cutoff p-type body
b
K.Moorthi AP/ECE
NMOS LINEAR
• Channel forms Vgs > Vt Vgd = Vgs
g
+ +
• Current flows from -s -
d
p-type body
• Ids increases with Vds b
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NMOS SATURATION
n+ n+
V ds > V gs -Vt
p-type body
b
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IDEAL I-V CHARACTERISTICS
• MOS transistor have three regions of operation:
1. cutoff region
2. Linear or non saturation region
3. Saturation region
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C-V CHARACTERISTICS
Where,
•MOS gate sits above the channel and overlap S & D diffusion
areas. Therefore, the Cg has 2 components:
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DETAILED MOS GATE CAPACITANCE cont…..
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DETAILED MOS GATE CAPACITANCE cont…..
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DETAILED MOS DIFFUSION CAPACITANCE MODEL:
•Reverse biased p-n junction b/w the S diffusion & the body
contributes parasitic capacitance ant it depends on both area
AS & sidewall perimeter PS of the S diffusion region.
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K.Moorthi AP/ECE
Non ideal I-V effects
• The ideal I-V model neglects many effects that are
important to modern devices.
Ids (A)
Simulated
Vgs = 1.0
Ideal
1200
Velocity saturation & Mobility degradation:
Ion lower than ideal model predicts
1000
Ion = 747 mA @
Channel length modulation: V = V = V
gs ds DD
Saturation current increases
800 with Vds Vgs = 1.0
Vgs = 0.8
600
Velocity saturation & Mobility degradation:
Vgs = 0.8
Saturation current increases less than
400 quadratically with Vgs
Vgs = 0.6
200 Vgs = 0.6
Vgs = 0.4
0 Vds
0 0.2 0.4 0.6 0.8 1
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Velocity Saturation & Mobility Degradation
• At high lateral field strengths (Vds/L), carrier velocity
ceases to increase linearly with field strength. This is
called velocity Saturation.
n L n
+ Leff +
p GND bulk Si
K.Moorthi AP/ECE
Channel Length Modulation
Vt 1 Vds
2
I ds V gs
2
= channel length modulation coefficient
not feature size
Empirically fit to I-V characteristics
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Body Effect
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Subthreshold Conduction
• Several sources of leakage resulting in current flow in
nominal off transistors.
• Vgs<Vt , the current drops off exponentially rather than
abruptly becoming zero. This is called subthreshold
conduction.
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Junction Leakage
• The source and drain diffusions are reverse-biased
diodes and also experience junction leakage into the
substrate or well.
p+ n+ n+ p+ p+ n+
n well
p substrate
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Tunneling
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Temperature Sensitivity
• Increasing temperature
– Reduces mobility
– Reduces Vt
• ION decreases with temperature
• IOFF increases with temperature
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CMOS TECHNOLOGIES
• The four main CMOS technologies
n-Well process
p-Well process
Twin-tub Process
Silicon on Insulator
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Fabrication process of a simple metal
oxide semiconductor (MOS) transistor
field oxide
oxide gate oxide
source drain
silicon substrate gate oxide
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The manufacture of a single MOS
transistor begins with a silicon
substrate.
silicon substrate
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A layer of silicon dioxide (field oxide)
provides isolation between devices
manufactured on the same substrate.
field oxide
oxide
silicon substrate
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Photoresist provides the means for
transferring the image of a mask
onto the top surface of the wafer.
photoresist
oxide
silicon substrate
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Ultraviolet light exposes
photoresist through windows in a
photomask.
Ultraviolet Light
Chrome plated
glass mask
Shadow on
photoresist
Exposed area of
photoresist
photoresist
oxide
silicon substrate
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Exposed photoresist becomes
soluble and can be easily removed
by the develop chemical.
photoresist
oxide
silicon substrate
K.Moorthi AP/ECE
Unexposed photoresist remains on
surface of oxide to serve as a
temporary protective mask for areas of
the oxide that are not to be etched.
Shadow on
photoresist photoresist
photoresist
oxide
silicon substrate
K.Moorthi AP/ECE
Areas of oxide protected by
photoresist remain on the silicon
substrate while exposed oxide is
removed by the etching process.
photoresist
oxide oxide
siliconsubstrate
silicon substrate
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The photoresist is stripped off --
revealing the pattern of the field oxide.
field oxide
oxide oxide
siliconsubstrate
silicon substrate
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A thin layer of oxide is grown on the
silicon and will later serve as the gate
oxide insulator for the transistor being
constructed.
gate oxide
oxide oxide
silicon substrate
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The gate insulator area is defined by
patterning the gate oxide with a
masking and etching process.
gate oxide
oxide oxide
silicon substrate
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Polysilicon is deposited and will
serve as the building material for
the gate of the transistor.
gate oxide
gate oxide
polysilicon
oxide oxide
silicon substrate
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The shape of the gate is defined
by a masking and etching step.
ultra-thin
gate oxide
polysilicon
gate
gate
oxide gate oxide
silicon substrate
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Dopant ions are selectively implanted
through windows in the photoresist mask.
ion beam
Scanning direction of
ion beam
implanted ions in active
region of transistors
photoresist
Implanted ions in
photoresist to be
removed during
resist strip.
gate
oxide gate oxide
source drain
silicon substrate
K.Moorthi AP/ECE
The source and drain regions of the
transistor are made conductive by
implanting dopant atoms into
selected areas of the substrate.
doped silicon
gate
oxide gate oxide
source drain
silicon substrate
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A layer of silicon nitride is deposited
on top of the completed transistor to
protect it from the environment.
top nitride
gate
source drain
silicon substrate
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Holes are etched into selected
parts of the top nitride where
metal contacts will be formed.
contact holes
gate
source drain
silicon substrate
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Metal is deposited and selectively
etched to provide electrical contacts
to the three active parts of the
transistor.
metal contacts
field oxide
oxide gate oxide
source drain
silicon substrate gate oxide
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P-Well process
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The twin-tub process
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The twin-tub process
Advantages:
1. Both n-well and p-well are fabricated on single n-
type substrate.
2. Possible to tune independently threshold voltage,
body effect..
3. Separate optimization of the p-type & n- type
transistors.
Disadvantages:
1. Requires lot of mask
2. Complex
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Silicon on Insulator
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• Sapphire substrate
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• SOI Devices are categorized as Partially depleted(PD) or
fully depleted(FD).
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• Floating Body Voltage:
If the body voltage were constant, the threshold
voltage would be constant and the transistor would
behave much like conventional bulk device except
that the diffusion capacitance is lower.
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CMOS Fabrication
• CMOS transistors are fabricated on silicon
wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process
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Inverter Cross-section
• Typically use p-type substrate for nMOS
transistors
• Requires n-well for body of pMOS transistors
A
GND VDD
Y SiO2
n+ diffusion
p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1
K.Moorthi AP/ECE
Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
• Use heavily doped well and substrate contacts / taps
A
GND VDD
Y
p+ n+ n+ p+ p+ n+
n well
p substrate
well
substrate tap
tap
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Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line
GND VDD
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Detailed Mask Views
• Six masks n well
– n-well
– Polysilicon Polysilicon
– n+ diffusion n+ Diffusion
– p+ diffusion p+ Diffusion
– Contact Contact
– Metal
Metal
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Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
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Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
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Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2
p substrate
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Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist
Photoresist
SiO2
p substrate
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Etch
• Etch oxide with hydrofluoric acid (HF)
• Only attacks oxide where resist has been
exposed
Photoresist
SiO2
p substrate
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Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step
SiO2
p substrate
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n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
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Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps
n well
p substrate
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Polysilicon
• Deposit very thin layer of gate oxide
• Chemical Vapor Deposition (CVD) of silicon
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
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Polysilicon Patterning
• Use same lithography process to pattern
polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
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Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact
n well
p substrate
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N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
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N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion
n+ n+ n+
n well
p substrate
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N-diffusion cont.
• Strip off oxide to complete patterning step
n+ n+ n+
n well
p substrate
K.Moorthi AP/ECE
P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact
p+ Diffusion
p+ n+ n+ p+ p+ n+
n well
p substrate
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Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed
Contact
n well
p substrate
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Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+ n+ n+ p+ p+ n+
n well
p substrate
K.Moorthi AP/ECE
Layout Design Rules
• Layout design rules describe how small features can be
and how closely they can be packed in a particular
manufacturing process.
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Simplified λ based design rules
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• Inverter with dimensions Labeled
Transistor dimensions are often specified by their
Width/length(W/L) ratio.
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Gate Layout
• For many applications, a straight forward layout is good
enough and can be automatically generated or rapidly
built by hand.
• The power and ground lines are often called supply rails.
Polysilicon lines run vertically to form transistor gates.
Metal wires within the cell connect the transistors
appropriately.
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• Inverter standard cell layout
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Design Rules Background
• Well Rules:
The n-well is usually a deeper implant than the
source/drain implants, and therefore, it is
necessary for the outside dimension to provide
sufficient clearance between the n-well edge.
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K.Moorthi AP/ECE
• Contact Rules:
• There are several generally available contacts:
– Metal to p-active(p-diffusion)
– Metal to n-active(n-diffusion)
– Metal to polysilicon
– Metal to well or substrate
• The substrate is divided into well regions, each
isolated well must be tied to appropriate supply
voltage. nwell-must be tied to Vdd and the
substrate or pwell must be tied to GND with well
or substrate contacts.
• Metal makes a poor connection to the lightly
doped substrate or well. Hence, a heavily doped
active region is placed beneath the contact.
• Contacts are normally of uniform size.
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K.Moorthi AP/ECE
• Metal Rules:
• Metal spacing may vary with the width of the
metal line.
• Spacing rules that are applied to long, closely
spaced parallel metal lines.
• Scribe Line:
• The Scribe line surrounds the completed chip
where it is cut with diamond saw. The
construction of the scribe line varies from
manufacturer to manufacturer.
• It is designed to prevent the entry of contaminants
from the side of the chip.
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Technology related CAD issues
Two basic checks have to be completed to ensure that
this description can be turned into a working chip.
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• Design Rule Check:
Program to determine what we have designed by
examining the interrelationship of the various mask
layers, it may be necessary to determine various logical
between masks.
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The following Layers will be assumed as inputs
nwell
active
p-select
n-select
poly
poly-contact
active-contact
metal
Typically, useful sublayers are first generated.
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• To find the transistors, the following rule set is used:
CIRCUIT EXTRACTION:
To determine the electrical connectivity of a mask
database, the following commands are required.
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• The connections Between the layers can be specified as
follows:
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DC Transfer Characteristics
• DC Response
• Beta Ratio effects
• Noise Margins
• Pass Transistors K.Moorthi AP/ECE
DC Response
• DC Response: Vout vs. Vin for a gate
• Ex: Inverter
– When Vin = 0 -> Vout = VDD
– When Vin = VDD -> Vout = 0 VDD
– In between, Vout depends on
Idsp
transistor size and current Vin Vout
Idsn
– By KCL, must settle such that
Idsn = |Idsp|
– We could solve equations
– But graphical solution gives more insight
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Transistor Operation
• Current depends on region of transistor
behavior
• For what Vin and Vout are nMOS and pMOS in
– Cutoff?
– Linear?
– Saturation?
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nMOS Operation
Cutoff Linear Saturated
Vgsn < Vtn Vgsn > Vtn Vgsn > Vtn
Vin < Vtn Vin > Vtn Vin > Vtn
Vdsn < Vgsn – Vtn Vdsn > Vgsn – Vtn
Vout < Vin - Vtn Vout > Vin - Vtn
VDD
Vgsn = Vin
Idsp
Vdsn = Vout Vin Vout
Idsn
K.Moorthi AP/ECE
pMOS Operation
Cutoff Linear Saturated
Vgsp > Vtp Vgsp < Vtp Vgsp < Vtp
Vin > VDD + Vtp Vin < VDD + Vtp Vin < VDD + Vtp
Vdsp > Vgsp – Vtp Vdsp < Vgsp – Vtp
Vout > Vin - Vtp Vout < Vin - Vtp
VDD
Vgsp = Vin - VDD Vtp < 0
Idsp
Vdsp = Vout - VDD Vin Vout
Idsn
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I-V Characteristics
• Make pMOS is wider than nMOS such that n
= p V gsn5
Idsn Vgsn4
-Vdsp Vgsn3
-VDD Vgsn2
Vgsp1 Vgsn1
Vgsp2 0 VDD
Vgsp3 Vdsn
Vgsp4 -Idsp
Vgsp5
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Current vs. Vout, Vin
Vin0 Vin5
Vin1 Vin4
Idsn, |Idsp|
Vin2 Vin3
Vin3 Vin2
Vin4 Vin1
VDD
Vout
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Operating Regions
• Revisit transistor operating regions VDD
Vin Vout
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Beta Ratio
• If p / n 1, switching point will move from
VDD/2
• Called skewed gate
• Other gates: collapse into equivalent inverter
VDD
p
10
n
Vout 2
1
0.5
p
0.1
n
0
VDD
Vin
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Noise Margins
• How much noise can a gate input see before it
does not recognize the input?
Output Characteristics Input Characteristics
VDD
Logical High
Output Range VOH Logical High
Input Range
NMH
VIH
Indeterminate
VIL Region
NML
Logical Low
Logical Low VOL Input Range
Output Range
GND
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Logic Levels
• To maximize noise margins, select logic levels at
– unity gain point of DC transfer characteristic
Vout
p/ n > 1
Vin Vout
VOL
Vin
0
Vtn VIL VIH VDD- VDD
|Vtp|
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Pass Transistors
• Transistors can be used as switches
s d g=1
g=0
s d 1 strong 1
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Transmission Gates
• Pass transistors produce degraded outputs
• Transmission gates pass both 0 and 1 well
Input Output
g = 0, gb = 1 g = 1, gb = 0
g
a b 0 strong 0
a b g = 1, gb = 0 g = 1, gb = 0
a b 1 strong 1
gb
g g g
a b a b a b
gb gb gb
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Tristate Inverter
• Tristate inverter- cascading transmission
gate with an inverter.
• EN=0 ,output-tristate condition.
EN=1, o/p= complement
A A
A
EN
Y Y Y
EN
EN = 0 EN = 1
Y = 'Z' Y=A
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