Design and Implementation of VLSI Systems

Lecture04

MOSFET
MOS transistor theory

• Schedule for 4 lectures

– Ideal (Shockley) Model
– Non-ideal model
– Inverter DC characteristics
– SPICE
gate-oxide-body sandwich = capacitor
polysilicon gate
Vg < 0
Operating modes +
silicon dioxide insulator
p-type body
• Accumulation -

• Depletion
(a)
• Inversion
0 < V g < Vt
depletion region
+
-

(b)

• The charge accumulated

is proportional to the V >V g t
inversion region
+
excess gate-channel - depletion region

voltage (Vgc-Vt)
(c)
Gate capacitance as a function of Vgs

QuickTime™ and a
decompressor
are needed to see this picture.
The MOS transistor has three regions of
operation
• Cut off
Vgs < Vt

• Linear (resistor):
Vgs > Vt & Vds < VSAT=Vgs-Vt
Current prop to Vds
NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD
= 2.5V, VT = 0.4V

• Saturation:
Vgs > Vt and Vds ≥ VSAT=Vgs-Vt
Current is independent of Vds
How to calculate the current value?
• MOS structure looks like parallel plate
capacitor while operating in inversion
– Gate – oxide – channel
• Qchannel = CV
• C = εoxWL/tox = CoxWL (where Cox=εox/tox)
• V = Vgc – Vt = (Vgs – Vds/2) – Vt

gate
Vg
+ +
source Vgs Cg Vgd drain
Vs - - Vd
channel
n+ - + n+
Vds
p-type body
Carrier velocity is a factor in determining the
current

• Charge is carried by electrons

• Carrier velocity v proportional to lateral E-field
between source and drain
• v = μE μ called mobility
• E = Vds/L
• Time for carrier to cross channel:
t = L / v = L / (μ Vds/L)
= L2 / (μ Vds)
I=Q/t
• Now we know
– How much charge Qchannel is in the channel
– How much time t each carrier takes to cross
Qchannel
I ds =
t
W V − V − Vds V
= Cox  gs  ds
L
t 2 
=  Vgs − Vt − ds Vds
V
 2
In linear mode (Vgs > Vt & Vds < Vgs-Vt)
Qchannel
I ds =
t
W V − V − Vds V
= Cox  gs  ds
L
t 2  Can be ignored for small Vds

=  Vgs − Vt − ds Vds
V
 2

➢For a given Vgs, Ids is proportional (linear) to Vds

In saturation mode (Vgs > Vt and Vds ≥ Vgs-Vt)
Qchannel
I ds =
t
W V − V − Vds V
= Cox  gs  ds
L
t 2 
=  Vgs − Vt − ds Vds
V
 2

I ds =  Vgs − Vt −
Vdsat V pinched off
2  dsat
 

( − Vt )
2
= V gs
2
➢Now drain voltage no longer increases current
Operation modes summary


 0 Vgs  Vt cutoff


I ds =   Vgs − Vt − ds V V  V
V
 ds linear
2 ds dsat
  
 
(Vgs − Vt )
2
 Vds  Vdsat saturation
2
Transistor capacitance

▪ Gate capacitance: to body + to drain + to source

▪ Diffusion capacitance: source-body and drain-body capacitances
Gate capacitance as a function of Vgs

QuickTime™ and a
decompressor
are needed to see this picture.
Source/Drain diffusion capacitance

• Csb, Cdb
• Undesirable, called parasitic
Channel-stop implant
capacitance N
A1

• Capacitance depends on area and Side wall

perimeter W Source
ND
– Use small diffusion nodes
Bottom
– Comparable to Cg
– Varies with process xj Side wall
Channel
LS SubstrateNA
Exercises

• A 90 nm long transistor has a gate oxide

thickness of 16 A. What is its gate capacitance
per micron of width?
Exercises

• A 90 nm long transistor has a gate oxide thickness of

16 A. What is its gate capacitance per micron of width?
Exercises

• A 90 nm long transistor has a gate oxide thickness of

16 A. What is its gate capacitance per micron of width?
Exercises

• Calculate the diffusion parasitic Cdb of the drain of a

unit-sized contacted nMOS transistor in a 0.6 µm
process when the drain is at 0 and at VDD = 5 V.
Assume the substrate is grounded. The transistor
characteristics are CJ = 0.42 fF/µm2, MJ =0.44, CJSW
= 0.33 fF/µm, MJSW = 0.12, and Ψ0 = 0.98 V at room
temperature. The minimum size of diffusion contact is
1.2x1.5 µm.
Exercises

• Calculate the diffusion parasitic Cdb of the drain of a

unit-sized contacted nMOS transistor in a 0.6 µm
process when the drain is at 0 and at VDD = 5 V.
Assume the substrate is grounded. The transistor
characteristics are CJ = 0.42 fF/µm2, MJ =0.44, CJSW
= 0.33 fF/µm, MJSW = 0.12, and Ψ0 = 0.98 V at room
temperature. The minimum size of diffusion contact is
1.2x1.5 µm.
Exercises

• Calculate the diffusion parasitic Cdb of the drain of a unit-sized

contacted nMOS transistor in a 0.6 µm process when the drain is
at 0 and at VDD = 5 V. Assume the substrate is grounded. The
transistor characteristics are CJ = 0.42 fF/µm2, MJ =0.44, CJSW =
0.33 fF/µm, MJSW = 0.12, and Ψ0 = 0.98 V at room temperature.
The minimum size of diffusion contact is 1.2x1.5 µm.
• Solution:
• The area = 1,8 µm2. Parameter = 5,4 µm2 => total capacitance:
Exercises

• Calculate the diffusion parasitic Cdb of the drain of a unit-sized

contacted nMOS transistor in a 0.6 µm process when the drain is
at 0 and at VDD = 5 V. Assume the substrate is grounded. The
transistor characteristics are CJ = 0.42 fF/µm2, MJ =0.44, CJSW =
0.33 fF/µm, MJSW = 0.12, and Ψ0 = 0.98 V at room temperature.
The minimum size of diffusion contact is 1.2x1.5 µm.
• Solution:
• The area = 1,8 µm2. Parameter = 5,4 µm2 => total capacitance:
Exercises

• Consider the nMOS transistor in a 0.6 µm

process with gate oxide thickness of 100A. The
doping level is NA = 2 × 1017 cm–3 and the
nominal threshold voltage is 0.7V. The body is
tied to ground with a substrate contact. How
much does the threshold change at room
temperature if the source is at 4 V instead of 0?
Exercises

• Consider the nMOS transistor in a 0.6 µm process with

gate oxide thickness of 100A. The doping level is NA =
2 × 1017 cm–3 and the nominal threshold voltage is
0.7V. The body is tied to ground with a substrate
contact. How much does the threshold change at room
temperature if the source is at 4 V instead of 0?
Exercises

• Consider the nMOS transistor in a 0.6 µm process with

gate oxide thickness of 100A. The doping level is NA =
2 × 1017 cm–3 and the nominal threshold voltage is
0.7V. The body is tied to ground with a substrate
contact. How much does the threshold change at room
temperature if the source is at 4 V instead of 0?
Exercises

An nMOS transistor has a threshold voltage of 0.4 V and a

supply voltage of VDD = 1.2 V. A circuit designer is
evaluating a proposal to reduce Vt by 100 mV to obtain
faster transistors.
a) By what factor would the saturation current increase (at
Vgs = Vds = VDD) if the transistor were ideal?
b) By what factor would the subthreshold leakage current
increase at room temperature at Vgs = 0? Assume n = 1.4.
c) By what factor would the subthreshold leakage current
increase at 120 °C? Assume the threshold voltage is
independent of temperature.
Exercises

An nMOS transistor has a threshold voltage of 0.4 V and a supply

voltage of VDD = 1.2 V. A circuit designer is evaluating a proposal to
reduce Vt by 100 mV to obtain faster transistors.
a) By what factor would the saturation current increase (at Vgs = Vds =
VDD) if the transistor were ideal?
b) By what factor would the subthreshold leakage current increase at
room temperature at Vgs = 0? Assume n = 1.4.
c) By what factor would the subthreshold leakage current increase at
120 °C? Assume the threshold voltage is independent of temperature.

I ds =  Vgs − Vt − dsat V
V
2  dsat
 

( − Vt )
2
= V gs
2
Exercises
Summary
• Covered ideal (long channel) operation (Shockley model) of
transistor
• Short-channel transistors
• TA