EEE/ INSTR F313

Analog Digital VLSI Design

BITS Pilani
Pilani Campus Anu Gupta
SHORT CHANNEL EFFECTS
Long channel device
• L>>> dep.1 + dep.2
• L>> Wdm
Short Channel Device
• L> dep.1 + dep.2-
• L ≈ Wdm or Xj --- short channel MOSFET
• L is comparable to MOS depletion width in
vertical direction.

• Source drain potential has strong effect on band

bending over a significant length of device
• S-D fields penetrate deeply in the middle of the
channel, lowering of s- d potential barrier
• Threshold voltage reduces
Non scaling parameters
• kT/q

• Eg/q

• Hence Wdm [vertical depletion width], built-in

potential, surface potential, inversion layer
thickness do not change appreciably

• But Vt degradation, offstate leakage

increases
Some scaling issues
• As Vt is very low, Isubthreshold increases
• As inversion layer thickness is unchanged, but Vt is
reduced, hence inversion charge density is less , so
current drive is less, so gm is less

• To keep off state leakage less, have higher Vt. so

current drive [ (Vgs-Vt)] is further less, so delay will
further increase
• To inc. current, if we take large Vdd, electric fields will
increase that will further trigger short channel effects
 HARD FACTS

• SDE source drain extension

 Major SCE
• DIBL (punch through)
• Mobility degradation due to surface
scattering — less drive current
• Carrier velocity saturation---high elec. Field
• Impact ionization
• Hot electron injection
• Oxide breakdown---- high elec. field
• Oxide leakage----biggest problem
These cause Vt roll off– leakage current
DIBL
• When depletion region surrounding the
drain extends to source
• Potential barrier in channel reduces,
electrons flow from source to drain even
at low Vgs
• Subthreshold current increases
 Punch-Through
L +V
xo D n-p-n BJT
rj rj
Ws WD

L
++V
xo S&D depletions touch
D
rj rj – punch through
Ws e- WD
DIBL
• Electrons can flow from source to drain (no more back to
back junctions) (n-channel enhancement mode)
• ID  VD2
– Resistor with decreasing resistance with drain voltage
(depletion overlap)
• Drain current no longer controlled by gate
• Drain current does not saturate
• Huge sub-threshold currents
• Transistors won’t “turn off”
• General “Cure” – high dose implant in sub-gate region to
make narrower depletion widths
• Higher substrate doping increases parasitic capacitances
Short Channel Effects – punch
through (pmos)
Surface scattering (mobility reduces)

• Depletion region extends more into

channel.
• Channel length further reduces,
longitudinal electric field Ey increase
• Inversion layer thinning occurs, electron
scattering takes place when electrons are
accelerated toward the interface by Ex
• So mobility reduces, less drive current
Carrier velocity saturation
 Velocity Saturation
the device enters saturation before VDS reaches VGS-VT.
Velocity Saturation
• Under high field conditions, carrier velocity independent of field
(terminal velocity)
• For 0.25 m technology (2.5V),
• E~ 2.5V/2.5x10-5cm =105 V/cm

I D  qnA n A=area
Qn n=carrier density
n x=channel thickness
qx n=carrier velocity
Qn  Ci (VG  VT )

(VG  VT ) n
I D  qZxCi
qx
I D  ZCi (VG  VT ) n I D sat  ZCi (VG  VT ) sat
Velocity Saturation Effect – surpressed drain current

ID
g m sat   ZCi  sat  const.
VG sat

Measurement Calculation with Calculation w/o

Velocity Saturation Velocity Saturation
Velocity Saturation (2)

1.5 0.5
VGS = 5

Linea r Dependence
1.0 VGS = 4

ID (mA)
I D (mA)

VGS = 3
0.5
VGS = 2
VGS = 1
0
0.0 1.0 2.0 3.0 4.0 5.0 0.0 1.0 2.0 3.0
VDS (V) VGS (V)

(a) I D as a function of VDS (b) ID as a function of VGS

(for VDS = 5 V).

Linear Dependence on VGS

 Hot electrons -Oxide Charging
• Carriers accelerated toward Drain/depletion can have
sufficient energy to escape into the oxide
• Neutral traps (defects) in the oxide trap charge
• Leads to long term shift in characteristics in long-channel
• Short-channel – more of the gate oxide is near the drain –
big effect – big VT and gm effects - device failure

n-
n+
Hot Electron
Why Vt roll off?
Sub-Threshold Conduction

102

104 Linear region

106
ln(ID) (A)

108

1010 Subthreshold exponential region

10120.0
VT 1.0 2.0 3.0
VGS (V)
Sub-Threshold Conduction
Parasitic Resistances
How to continue scaling MOS?
2 issues
• Less gate leakage--use thicker gate oxide
or a material had to be physically thick but
electrically thin

• We should be able to scale down Vt with

less off-state leakage. Hence, we should
be able to scale L with preserved electric
field contours
Prob.-1-- Gate leakage
• The goal was to identify a gate dielectric that
leaked less while at the same time driving plenty
of current across the transistor channel.

• We need a gate insulator that is

thick enough to keep electrons from tunneling through
it and
yet permeable enough to let the gate's electric field
into the channel
so that it could turn on the transistor.
Which one?
• aluminum oxide (Al2O3),
• titanium dioxide (TiO2),
• tantalum pentoxide (Ta2O5),
• hafnium dioxide (HfO2), [electrically stable , and good compatibility with silicon]
• hafnium silicate (HfSiO4),
• zirconium oxide (ZrO2),
• zirconium silicate (ZrSiO4),
• and lanthanum oxide (La2O3).
 Gate leakage---continued
• The technical term for such a material is a “high-k” dielectric;
k,

• The dielectric constant, is a term that refers to a material's

ability to concentrate an electric field. Having a higher
dielectric constant means the insulator can provide increased
capacitance between two conducting plates—storing more
charge—for the same thickness of insulator.

• Or it can provide the same capacitance with a thicker insulator

 Reduce Vt--Well engineering
• By changing the doping profile in the channel region, the
distribution of the electric field and potential contours can be
changed.

• The goal is to optimize the channel profile to minimize the off-

state leakage while maximizing the linear and saturated drive
currents.

• Super Steep Retrograde Wells (SSRW) and halo implants

have been used as a means to scale the channel length and
increase the transistor drive current without causing an
increase in the off-state leakage current
Prob. 2---Reduce Vt but less leakage
well/channel engineering
• We decrease Vt by using non uniform
doping profile
• Low high doping [SSRW]— retrograde
doping
SSRW

Multiple implant steps including retrograde

high energy Boron retrograde well implant
Less leakage at less Vt
• Typically , higher threshold voltages (for 1nA leakage
current) are required for smaller gate lengths [due to the
increase in channel doping] to control off state leakage

• SSRW architecture supports smaller channel lengths

compared to the uniform well case for all threshold
voltages
SSRW
• Retrograde Implant

• High energy implants put peak ion concentration deep in

substrate

• RTA to activate dopants rather than long drive-in

diffusion – higher packing density

• Reduces “latch-up” in CMOS and “soft errors” in DRAM

• Allows separate implants for threshold adjust, anti-

punchthrough, and latch-up(well)
Control high electric fields at drain

• High Nd, low xj, small L high E at drain

• RemedyShallow, lightly doped Source

drain extensions to lessen drain control
on channel charge
Impact of shallow junctions

potential contours extend

much further into the
channel
for the device with the
deep junction.

Reducing SDE junction depths improves device short-channel

characteristics by reducing the amount of channel charge controlled
by the drain. To reduce E at drain , reduce Nd, x
E= qNd x
Drawback
• But reduced Nd entirely  high s/d
resistance

• Less xj small overlap between gate and

drain
Source drain extensions
• S/ D junctions can’t be shallow entirely

• This is because any improvement in short channel

effects due to reduced charge sharing is offset by a large
increase in external resistance and too small an overlap
between the SDE and gate.
• So LDD followed by deep N+ junctions
LDD
HALO

Local heavy substrate doping for punch-through control leaving

channel lightly doped for threshold control
Halo engineering
• Add additional well dopant around the source and
drain regions providing an increased source-to-
drain barrier for current flow.
• For short channel devices HALO implants reduce
off-state leakage. (to inc Vt with LDD)
Finfet
END
 Reverse short-channel effect
Reverse short-channel effect (RSCE) is a result of non-
uniform channel doping (halo doping ) in modern processes.
To combat drain-induced barrier lowering (DIBL), MOSFET
channels are more doped near the source and drain terminals to
reduce the size of the depletion region in the vicinity of these
junctions (called halo doping to describe the limitation of this
heavy doping to the immediate vicinity of the junctions).
At short channel lengths the halo doping of the source overlaps
that of the drain, increasing the average channel doping
concentration, and thus increasing the threshold voltage.
 Reverse short-channel effect
This increased threshold voltage requires a larger gate voltage for
channel inversion. However, as channel length is increased, the halo
doped regions become separated and the doping mid-channel
approaches a lower background level dictated by the body doping.

This reduction in average channel doping concentration means Vth

initially is reduced as channel length increases, but approaches a
constant value independent of channel length for large enough
lengths.
ESD Protection
• Human body carries charge
• Touching a conductor results in transfer of
charge –or static shock
• If we accidentally touch Cox, thinox may
get damaged
• To keep from damaging the Cox,
protection circuit is used
Human body model
ESD protection
Static voltage
ESD

• Carefully protect electrostatic protection devices

associated with I/O pads with guard rings.

• Electrostatic discharge can trigger latchup. ESD

enters the circuit through an I/O pad, where it is
clamped to one of the rails by the ESD
protection circuit.

• Devices in the protection circuit can inject

minority carriers in the substrate or well,
potentially triggering latchup.
Contd.

• Radiation, including x-rays, cosmic, or

alpha rays, can generate electron-hole
pairs as they penetrate the chip. These
carriers can contribute to well or substrate
currents.
• Sudden transients on the power or ground
bus, which may occur if large numbers of
transistors switch simultaneously, can
drive the circuit into latch-up. Whether this
is possible should be checked through
simulation.
Device models

Shd. be more accurate to obtain

reliable simulation results
Accurate device models

To get reliable simulation results

SPICE MODELS

Level 1: Long Channel Equations - Very Simple

Level 2: Physical Model - Includes Velocity

Saturation and Threshold Variations

Level 3: Semi-Emperical - Based on curve fitting

to measured devices

Level 4 (BSIM): Emperical - Simple and Popular

Fitting level-1 model for manual analysis

Region of
matching
ID
Short-channel
I-V curve
VGS = 5 V

Long-channel
approximation

VDS = 5 V VDS

Select k’ and  such that best matching is obtained @ Vgs= Vds = VDD
Technology Evolution
Process Variations
Devices parameters vary between runs and even on
the same die!
Variations in the process parameters, such as impurity concentration den-
sities, oxide thicknesses, and diffusion depths. These are caused by non-
uniform conditions during the deposition and/or the diffusion of the
impurities. This introduces variations in the sheet resistances and transis-
tor parameters such as the threshold voltage.
Variations in the dimensions of the devices, mainly resulting from the
limited resolution of the photolithographic process. This causes (W/L)
variations in MOS transistors and mismatches in the emitter areas of
bipolar devices.
Impact of Device Variations

2.10
2.10

1.90

Delay (nsec)
Delay (nsec)

1.90

1.70
1.70

1.50 1.50
1.10 1.20 1.30 1.40 1.50 1.60 –0.90 –0.80 –0.70 –0.60 –0.50

Leff (in mm) VTp (V)

Delay of Adder circuit as a function of variations in L and VT

Origin of SCE
Prob. in Sub-Micron MOS Transistor

• Threshold Variations

• Parasitic Resistances

• Velocity Sauturation and Mobility Degradation

• Subthreshold Conduction

• Latchup
Threshold Variations

VT

Long-channel threshold Low VDS threshold

Threshold as a function of Drain-induced barrier lowering

the length (for low VDS) (for low L)
• The quest for the highest efficiency, reliability and lowest
footprint are at the top of the power designer’s priority list