Physics of VLSI Devices –

MVLD501L (Module 5)
Dr. Rajan Pandey
Associate Professor, SENSE
 Parasitic Source-Drain Resistance Current in the
I dsat 0 absence of Rs
• Idsat0  Vg – Vt , I dsat 
I R This factor should
1  dsat 0 s
Short channel MOSFET (Vgs  Vt ) be dimension-less.
It is ignorable
• Idsat can be reduced by about 15% in a 0.1 µm (100 nm) MOSFET. when Rs is small.
Effect is greater in shorter MOSFETs.
• A second effect is an increase in Vdsat :
Vdsat = Vdsat0 + Idsat (Rs + Rd)
where Vdsat0 is the Vdsat in the absence of Rs and Rd.

• What causes the S/D parasitic resistance?

• The shallow diffusion region under the dielectric spacer is a contributor to the parasitic resistance.
• Why shallow diffusion region is needed at first place?
• The shallow junction is needed to prevent excessive off-state leakage Ids in short channel transistors.
• The contact resistance is another main source of resistance.
• The silicide (e.g., TiSi2 or NiSi2) reduces the sheet resistivity of the N+ (or P+) source–drain regions by
a factor of ten.
• It also reduces the contact resistance between the silicide and the N+ or P+ Si.
 SALICIDE (Self-Aligned Silicide) Source/Drain

• After the spacer is formed, a Ti or Ni or Mo film is deposited.

• Annealing causes the silicide to be formed over the source, drain, and gate.

• Unreacted metal (over the spacer) is removed by wet etching.

Definitions of • A circuit designer specifies a channel length in the circuit layout, called
Channel Length the drawn gate length, Ldrawn.

• This layout is transferred to a photomask, then to a photoresist pattern,

and finally to the physical gate.

• The final physical gate length, Lg, may not be equal to Ldrawn because
each pattern transfer can introduce some dimensional change.

• Through Optical Proximity Correction (OPC) one can minimize the

difference between Ldrawn and Lg.

• For device analysis and modeling, it is necessary to know the channel

length, L, or effective channel length (Leff) or electrical channel length
(Le) to differentiate it from Ldrawn and Lg.

• The difference between Ldrawn and L is ∆L.

• Ldrawn, Lg, and L (also known as Leff or Le) are different in general.
• How do we measure Lg?
• Through scanning electron microscopy (SEM).
L  Ldrawn  L • What about ∆L? How do we find it?
 Extraction of the Series Resistance and the Effective Channel Length

L  LDrawn  L Measuring ∆L in short transistors is quite difficult.

However, we can graphically estimate it…
WCoxe  sVds
I ds  (Vgs  Vt )
Ldrawn  L
I ds ( Ldrawn  L)
Vds 
WCoxe (Vgs  Vt )  s

Include series resistance,

Rds  Rd + Rs ,
Vds Ldrawn  L
 Rds  y = mx + c
I ds WCoxe (Vgs  Vt )  s

= Rds + channel resistance

S/D parasitic resistance Method of extracting Rds and ∆L
 Interpretation of channel length and its dependence on Vg
The channel length may be interpreted
as the length of the part of the channel The channel is where the conductivity
where the inversion-layer sheet is determined by Vg, not by the
conductivity is larger than the source–drain doping profiles.
source/drain sheet conductivity.

The inversion-layer sheet The channel expands (i.e., L increases

conductivity increases and Rds decreases) with increasing Vg.
with increasing Vg.

Due to increase in the sheet

Any resistance from outside the conductivity
“channel” is attributed to Rds.
 Velocity Overshoot
• The velocity saturates at high field. In the basic
velocity-saturation model, vsat is independent of the
channel length. The data shows that vsat becomes
larger when L is very small.

• When the channel length is sufficiently small, the

electrons may pass through the channel in too short
a time for all the energetic carriers to lose energy by
emitting optical phonons.

• As a result, the carriers can attain somewhat higher

velocities in very small devices. This phenomenon is
• Velocity saturation should not occur in very called velocity overshoot. (Note temperature is low.)
short MOSFETs! Why?
• Velocity overshoot frees the extremely short
• Because velocity overshoot could lift the limit transistors from the limit of velocity saturation.
on Ids. (Thus, mitigate the velocity saturation.) But…….  we have something else that limits…..
 Velocity Overshoot

• The concept of mobility is questionable when the channel length is comparable to

or smaller than the mean free path. The carrier velocity at the drain end of the
channel is limited by the saturation velocity, which determines Idsat.

• When the channel length is reduced much below 100 nm, the saturation velocity
may be greatly raised by velocity overshoot. In that case, some other limit on Idsat
may set in. What is that?
 Source Velocity Limit
Short channel • Idsat = WBvthxQinv
MOSFET
= WBvthxCoxe(Vgs – Vt)
• This is similar to
B is the fraction of carriers
captured by the drain in a real
transistor. The rest of the
injected carriers are scattered
back toward the source.

I dsat  Wvsat C oxe (Vgs  Vt )

Except that vsat is replaced by vthx, the x-direction component of the

thermal velocity. vthx is about 1.6 x 107 cm/s for electrons and 1 x 107
cm/s for holes in Silicon MOSFETs.

The carrier velocity at the source becomes the limiting factor. There,
the velocity is limited by the thermal velocity, with which the
carriers enter the channel from the source. This is known as the
source injection velocity limit.
 Output Conductance
• Idsat does NOT saturate in the saturation region, especially in short channel devices!
• The slope of the Ids-Vds curve in the saturation region is called the output conductance
(gds), 0.4
L = 0.15 m
V gs = 2.5V
Vt = 0.4 V
0.3

I ds (mA/m)
V gs = 2.0V

dI 0.2
g ds  dsat V gs = 1.5V
dVds 0.1 V gs = 1.0V

0.0
0 1 2 2.5
V ds (V)

• The physical cause of the output conductance is the influence of Vds on Vt and a
phenomenon called channel length modulation.
• A smaller gds is desirable for a large voltage gain, which is beneficial to analog and
digital circuit applications. Let us see this in an example…
 Example of an Amplifier
• The transistor operates in the saturation region. A small signal input, vin, is applied.
ids  g msa t  gs  g ds  ds
 g msa t  in  g ds  out Vdd

R
Also,  out  ids R
out
in
g msat
Eliminating ids  out    in NFET
( g ds  1 / R )

• The voltage gain is vout /vin = gmsat/(gds + 1/R).

• A smaller gds is desirable for large voltage gain. gds must be kept much lower than gmsat.
• The gain can also be increased by using a large R.
• Maximum available gain is gmsat/gds, also called intrinsic voltage gain (for very large R).