EEE 202

ELECTRONIC CIRCUIT II
MOS REVIEW AND MODELS

Dr. Mohammad Mojammel Al Hakim

MOSFET Introduction
History

A conceptually similar structure to a modern field effect transistor (FET) was first
proposed and patented by Lilienfeld and Heil in 1930, but was not successfully
demonstrated until 1960. In 1962 the first commercial integrated circuit (IC) with 16
metal-oxide-semiconductor FETs (MOSFETs) was produced and 1965 the first calculator
based on a MOS IC was commercialized. During only 35 years the device dimensions
have shrunk by a factor of almost 10000 and the integration scale has increased by a
factor of 1 million, however, the basic technology based on a planar process has remained
the same.
The main technological problem in early devices was the control and reduction of the
surface states (fixed charges) at the interface between the oxide and the semiconductor.
Initially, it was only possible to deplete an existing n-type channel by applying a negative
voltage to the gate. Such devices have a conducting channel between source and drain
even when no gate voltage is applied and are called "depletion-mode" devices. They are
of little practical use today. A reduction of the surface states enabled the fabrication of
devices which do not have a conducting channel unless a positive voltage is applied to
the controlling terminal (the gate). Such devices are referred to as "enhancement-mode"
devices. The electrons at the oxide-semiconductor interface are concentrated in a thin
(~10 nm thick) "inversion" layer. By now, almost all MOSFETs are "enhancement-
mode" devices.

Advantages

A MOS transistor (MOST) has several advantages over bipolar transistors: It can be
produced in a very reliable manufacturing process and a single transistor requires very
little space on a silicon wafer. This enables the ultra large scale integration of millions of
transistors on a modern microchip. A MOST is a device that is controlled by an electric
field and consequently has virtually no input current into the control terminal(s) (around
10-15 A) which also means that the input impedance is very high (up to several T). In
comparison to a bipolar transistor a MOST is a simpler device since it relies only on
majority carrier flow.

MOSFET Structure

Fig. 1 shows a n-channel MOSFET (In this course mainly n-channel MOSFET will be
discussed, for p-channel devices the polarity of all voltages have to be reversed). The
device is built into a positively doped silicon substrate and comprises two highly
negatively doped regions, the source and drain, a thin silicon dioxide (SiO2) layer
isolating a metal gate contact from the substrate. In modern devices the gate metal is
often replaced by polysilicon. A MOSFET is a four terminal device, gate, source, drain
and bulk (or substrate). It is a symmetrical device, there is no physical difference between

2
 Fig.1: MOSFET structure. (© Sedra and Smith [1])
source and drain. The drain node of a NMOST is defined as the node with the higher
potential of the two nodes. The region underneath the gate is called the channel, the
distance between drain and source is the channel length. If an appropriate voltage is
applied to the gate a conducting channel between the source and the drain is formed.
Electrons are flowing from the source to the drain, however, since the technical current
direction is opposite to the physical in a circuit diagram the current direction is shown
from drain to source.

Currently, transistors with channel length of 0.13m are commercialised, the gate oxide
is only a few nm thick. However these devices are only practical for digital circuits,
analogue circuits usually use channel length around 0.5 – 2m.

Operating Principle

Consider fig. 2, if the gate, source and bulk contacts are grounded and the drain contact
potential is positive or zero, the drain and source n+ regions are separated by two back-
to-back reverse biased diodes to the p-type substrate, thus there is no current flow and the
input impedance is very high (about 1012 Ω).

Next, we assume that drain and source are grounded and there is a positive voltage
applied to the gate as illustrated in fig. 2 (the substrate is always connected to the most
negative potential in the circuit and will not be explicitly mentioned in the following
discussion). The gate voltage will repel free holes in the p-type substrate, thus a region
with bound, uncovered negatively charged acceptor atoms is created i.e. a depletion

3 principle. (© Sedra and Smith [1])

Fig.2: MOSFET structure illustrating the operating
 region. Additionally, the positive gate voltage attracts electrons from the n+ drain and
source regions into the channel region. When a sufficient number of electrons accumulate
near the surface of the substrate under the gate, effectively a n-region is created in the p-
substrate creating a conducting channel between source and drain. The gate voltage
required to form a channel is called the threshold voltage Vt. If now a voltage, vDS, is
applied between the drain and gate a current, iD, will flow which is maintained by mobile
electrons. Since the gate terminal is insulated from the channel by the gate oxide the
drain current is the same as the source current.

Triode (or linear or ohmic) region: For small vDS a current will flow in the
channel from drain to source if a channel exists. iD depends on the density of electrons in
the channel which, in turn, depend on vGS. Also, if vGS increases the channel will extend
further into the substrate. Thus, the conductance of the channel increases; to first order it
is proportional to (vDS – Vt). Effectively, the MOSFET is behaving as a linear resistor
whose value is controlled by vGS. The situation in the triode region is illustrated in fig. 3.
Fig. 3a shows that the channel is assumed to be of uniform depth across the channel, this
is the usual assumption made for small vDS. It should be noted here that this is only an
approximation: imagine wandering along the channel from source to drain. The source
potential is zero, the drain potential is positive, but small compared to vG. At the source
end the voltage drop from gate to source is vGS = vG since vS=0. At the drain end the
voltage drop is vGD = vG - vD < vGS. Consequently, the channel extends further into the
substrate at the source end compared to the drain end. In between, along the channel, the
voltage is linearly decreasing from vGS to vDS, since the channel depth is proportional to
the voltage drop, the channel depth is linearly decreasing from source to drain, too.
However, this effect is usually ignored for a MOSFET operating in the triode region, yet
it becomes dominant for larger vDS as will be explained in the next section.

iD [mA]
vGS = vt + 4V
vt = 1 V
vds small vGS = vt + 3V

vGS = vt + 2V

vGS = vt + 1V
vGS < vt

Fig 3a: MOSFET operating in triode region, i.e. v DS Fig 3b: Drain current as a function of v DS in triode
small (© Sedra and Smith [1]). region. The transistor behaves like a resistor with its
value determined by vGS (based on © Sedra and
Smith [1]).

4
 Saturation region: If vDS is becoming considerably larger than vGS the effect
that the channel has a tapered shape can not longer be ignored (see fig. 4). Eventually,
vGD becomes smaller than the threshold voltage, Vt, the channel vanishes at the drain end
and is said to be pinched off. The current iD reaches a maximum at this saturation point
and, to first order approximation, does not increase any more if vDS is increased further;
saturation is reached. This happens when vDS = vGS - Vt and is called the saturation
voltage, vDS,Sat. Further increase in vDS will result in moving the pinch-off point towards
the source hence the effective length of the channel is reduced. This channel length
modulation has some influence on iD which will be discussed later. The transition from
triode to saturation region is illustrated in fig. 5.

This operating region of a MOSFET is called the saturation region and is the region
mainly used for analogue circuit design. The transistor effectively behaves like a voltage
controlled current source with the gate as the controlling node.

Fig. 4: MOSFET with a tapered channel. Since the

voltage drop across the channel is smaller at the
drain, the channel is shallower at the drain end (©
Sedra and Smith [1]).

Fig. 5: In the linear region the channel is assumed to be of

uniform depth; the MOSFET behaves like a resistor (a). In (b)
the MOSFET is entering saturation region where the channel is
pinched off at the drain end. Further increase in v DS causes the
pinch-off point to move towards the source (c) (© Sze [2]).

Fig. 6: First order approximation of the iD – vDS

characteristics (© Sedra and Smith [1]).

5
Fig. 6 shows a first order approximation of the iD – vDS transistor characteristic.
Obviously, there is a transition region between the MOSFET operating in triode and
saturation region. For practical circuit design this region is usually avoided, typically a
transistor is biased about 200mV above vDS,Sat.

MOSFET Large Signal Characteristics

In the following the equations for the triode and saturation operating region will be
derived. For the symbols used in the calculations refer to fig. 7 showing a MOSFET in
triode region with a uniform channel.

Fig. 7: MOSFET in triode region. Refer to the symbols in the diagram

for the calculations below (© Gray and Meyer [3]).

Triode region vDS < vGS - Vt:

At a distance y away from the source, the voltage in the channel is v(y) and the gate to
channel voltage is vGS – v(y) which is assumed to be larger than the threshold voltage,
hence a channel exists at this point.

First, we have to calculate the charge per unit area (‘starred’ symbols refer to quantities
per unit area) in an infinitesimal small portion of the channel dy at a position y. The gate
oxide can be regarded as the dielectric of a parallel plate capacitor. However, the
difference to a ‘normal’ capacitor is that charge is only accumulated if the voltage drop is
larger than the threshold voltage hence the charge in this infinitesimal small portion of
the channel per unit area is given by:

dQ*(y) = Cox·(vGS – v(y) – Vt) [1]

6
v(y) is the potential difference between the channel at position y and the drain.

The area this charge is referred to is given by AQ = W·dy where W is the width of the
transistor. We also need to calculate the resistance of this infinitesimal small portion of
the channel. In order to do this, recall the basic equation for resistivity ρ:

ρ = 1/(n·q·n) [2]

where n is the carrier density (electrons in this case) per unit volume, q the electron
charge and n the electron mobility.

The resistance of a channel portion dy is given by:

dR = ρ·dy/Ach [3]

where Ach is the cross-sectional area of the channel given by x·W, x being the thickness
of the channel into the substrate.

Substituting eq.[2] in eq.[3] yields:

dR = dy/(x·W·n·q·n) [4]

Another way of expressing the charge per unit area in a portion dy of the channel is to
multiply the charge density per unit volume with the volume of the channel portion.
Obviously, the simplifying assumption of constant charge density across the entire
channel is made here:

dQ*(y) = dQ(y)/AQ = n·q·x·W·dy/(W·dy) = n·q·x [5]

Solving for n·q and substituting into eq.[4] yields:

dR = dy/(dQ*(y)·n·W) [6]

Next, we calculate the voltage drop along the channel portion dy which is simply given
by Ohm’s law and using eq.[6] and eq.[1] yields:

dv(y) = ID·dR = ID·dy/ dQ*(y)·n·W = ID·dy /( n·W·Cox·[vGS – v(y) – Vt]) [7]

It should be noted here that the current in the channel is the same at any point due to
current continuity, hence ID is independent of y.

Rearranging eq.[7] and integrating on both sides:

L vDS

 I D dy =  COX  nW (vGS − v( y ) − Vt ) dv( y )

0 0
[8]

7
yields:

W 1 2 
I D = COX  n  (vGS − Vt )v DS − v DS  [9]
L 2 

This is the governing equation describing a MOSFET operating in triode region. Often
this equation is further simplified by making the approximation vDS << vGS-Vt and
introducing the so-called process transconductance parameter k’ = n·Cox measured in
units of [A/V2] (which has the significance that it is a SPICE parameter). This results in:

ID = k'
W
((vGS − Vt )vDS ) [10]
L
It is obvious that eq.[10] has the form ID = vDS/R where the value of R is a function of the
gate voltage. This confirms the earlier statement that the MOSFET behaves like a voltage
controlled resistor in triode region.

Saturation region vDS > vGS - Vt:

From the results above, the governing equation for a MOSFET operating in saturation
region can easily be derived. At the onset of saturation the charge per unit area close to
the source end of the channel becomes zero since the voltage drop from gate to drain is
equal to the threshold voltage. Evaluating eq.[1] at y = L with above condition:

dQ*(L) = Cox·(vGS – v(L) – Vt) = 0 and v(L) = vDS [11]

Solving for vDS, which is the saturation voltage, gives

vDS,Sat = vGS - Vt [12]

Substituting eq.[12] in eq.[9] results in the governing equation for a MOSFET in

saturation region:

W 2
 (vGS − Vt )(vGS − Vt ) − (vGS − Vt )  = k (vGS − Vt )2
1 1 'W
I D = COX  n [13]
L 2  2 L
which has the form ID = constant for a given vGS, so the transistor behaves like a voltage
controlled current source to first order approximation.

It cannot be overemphasized that above derivations are a very crude approximation of the
real physical behaviour of a MOSFET, this is especially true when the gate length L is
smaller than 1m as routinely used for modern processes for which above equations are,
in fact, pretty useless. In the following, we will discuss physical effects in MOSFETs that
are important for accurate model derivation and, where possible, incorporate them in the
analytical expressions.

8
The first effect is the channel modulation which we have already briefly mentioned
qualitatively before. The point in the channel at which the voltage drop between gate and
substrate is smaller than Vt and will move towards the source if vDS is increased beyond
the saturation voltage. Effectively, this reduces the channel length, so for the analytical
expressions an effective channel length Leff is introduced:

Leff = L – yp [14]

where yp is the distance from the pinch-off point to the drain. Now eq.[13] can be
modified to:

1 W
ID = k' (vGS − Vt )2 [15]
2 Leff
Since the pinch-off point moves with increasing vDS, i.e. yp = yp(vDS), the drain current in
saturation region is NOT constant but continues to increase with larger vDS. The slope of
this increase can be calculated by taking the derivative of the drain current with respect to
the drain-source voltage; from eq.[15] we obtain:

I D 2 dLeff 1 dy p
= − k ' 2 (vGS − Vt )
1 W
= ID [16]
vDS 2 Leff dvDS Leff dvDS

Analogous to the Early voltage for bipolar transistors, a channel length modulation
parameter λ is introduced:

1 ID ID dv
VA = = = = Leff DS [17]
 I D 1 dy p dy p
v DS ID
Leff dv DS

where the results from eq.[16] was used.

If we assume λ as constant we can re-write eq.[15] as

I D = k ' (vGS − Vt ) (1 + vDS )

1 W 2
[18]
2 L

This is equation for the saturation region that SPICE uses in the level 1 model. Analytical
derivation of λ (or the pinch-off point yp) is very complicated, if not impossible.
Consequently, λ is often extracted from measurement data on fabricated MOSFETs. The
channel length modulation parameter λ is a SPICE parameter; typical values are between
0.03V-1 to 0.005V-1. Decreasing the channel length will result in an increase in channel
length modulation.

9
Threshold voltage Vt:

The remaining unknown parameter in above equations is the threshold voltage Vt. So far
we had Vt only loosely defined as the voltage at which a channel is formed. In the
following a simple analytical expression for Vt will be derived. Consider fig. 8 which
shows a MOS capacitor (which is effectively like a MOSFET but without the n+ source
and drain regions) to which a small, positive voltage is applied.

Depletion XD Inversion
region layer

XD
XD XD
XD

Fig. 8: MOS diode with a positive voltage Fig. 9: MOS diode with a positive voltage
smaller than Vt applied to it (a); band larger than Vt applied to it (a); band diagram
diagram (b) and charge densities (c) (b) and charge densities (c)

This voltage will generate an electric field that pushes away free holes (majority carriers)
in the substrate and forms a depletion layer under the gate. Consequently, a negative
fixed space charge of acceptor atoms, QSC, is created (see fig. 8c) which can be calculated
as:

QSC=-qNAXD [19]

where NA is the doping concentration in the substrate and XD the depth of the depletion
layer. The energy bands bend downwards as shown in fig. 8b.

If the voltage across the MOS capacitor is increased further and the energy bands are bent
accordingly, eventually the Fermi level will lie closer to the conduction band as to the
valence band (see fig. 9b). This is, however, the characteristic of n-type silicon, so
effectively at the surface of the semiconductor a n-type region, the so-called inversion
layer, is created in which free electrons are accumulated. In a MOSFET this forms the
conducting channel between source and drain. However, just above the point at which
Ef=Ei the inversion layer is not very pronounced, this is usually referred to as weak
inversion. At the onset of strong inversion, the depletion layer depth reaches a maximum
XD,Max, further increase in the voltage across the capacitor does not cause a further growth
of the depletion layer but rather results in the accumulation of electrons under the gate.

10
Consider a more detailed band diagram as shown in fig. 10. Above we have defined what
in commonly referred to as ‘weak inversion’, so a definition for strong inversion is
required. A simple criterion is that the electron concentration at the surface is equal to the
doping concentration in the substrate. In other words this means that the distance between
Ei and Ef in the substrate has the same magnitude as at the surface of the semiconductor
as depicted in fig.10. The voltage required for this situation is the threshold voltage Vt.

By analogy with an abrupt one sided pn- SiO2

EC
junction we can calculate the maximum P-Si
depletion depth: Me Ei
qΦF
EF
2 Si S qΦS
qΦF
X D ,Max = [20] EV
qN A qVT
Onset of strong
inversion
where ΦS is the potential at the surface of the EF XDMax

semiconductor. From fig. 10 it is obvious that

the surface potential is twice below the Fermi
potential in the substrate, i.e. ΦS = 2ΦF. The
charge density per unit area in the depletion QM

area at the onset of strong inversion is thus: QN QSCMax=-qNaXDMax

Fig. 10: Band diagram of a MOSFET at

QD,Max = −qN A X D,Max = − 4qN A Si F [21] the onset of strong inversion.

The threshold voltage therefore comprises two terms: first a voltage that is associated
with the depletion charge QD which can be considered as stored charge on a capacitor
(the charge in the channel, QN at the onset on strong inversion is much smaller than QD
and hence is neglected) and a voltage that is required to bend the energy bands by 2ΦF.
Thus:

QD ,Max 4qN A Si F

Vt = − + 2 F = + 2 F [22]
Cox Cox

This equation is often rewritten in the form:

2qN A Si
Vt =  2 F + 2 F with  = [23]
Cox

γ is called the Body effect parameter (for reasons will become clear in the next sections)
and is a SPICE parameter since it depends only on fabrication process parameters.

The remaining unknown in eq.[23] is the Fermi potential ΦF which can be calculated
from the substrate doping concentration:

11
 Ei − EF qF
kT  N A 
p = N A = ni e kT
= ni e kT  F = ln   [24]
q  ni 

Work Function Difference

The work function of a material defined as the energy required to lift an electron from the
Fermi level to the vacuum energy level. In the above derivation of the threshold voltage
we did not consider that there is difference in the work function between the gate material
(metal or poly-silicon) and the silicon substrate i.e. we assumed that if there is no external

qΦM qΦSi

Fig. 11: Energy band diagrams for a MOSFET with no external voltage applied hence the
energy are bend by the work function difference (a) and with the flat band voltage applied (b).
voltage applied the energy bands in the semiconductor are not bend. The work functions
for Al or n+ Poly-Si are less than for p-type Si. Since the Fermi energy levels have to be
continuous for no external voltage, some band bending of the valence and conduction
bands has to occur, this is illustrated in fig. 11a. To make the bands flat an external
voltage has to be applied, this voltage is usually referred to as the flat-band voltage VFB
and is given by the difference in work function between gate and bulk material:

VFB = ΦG - ΦS [25]

Where ΦG is the work function of the gate material and ΦS the work function of silicon.

The equation for the threshold voltage has to be corrected by adding a term which is
equal to the difference in work function i.e. by the flat band voltage.

Trapped Oxide Charge

In the Si-oxide there is always a fixed or trapped oxide charge, QSS, located close to the
SiO2/Si interface due to non-ideal oxide growth during the fabrication process. Qss is
positive since there are unoxidized Si atoms in the SiO2. This charge will repel holes in
the p-type substrate thus making the formation of an inversion layer easier. Consequently,

12
the threshold voltage will be lowered and eq.[23] has to be corrected by a term -Qss/COX.
With these modification we obtain:

VT = ΦGS - Qss/COX + 2ΦF + γ sqrt(2ΦF) [26]

Body Effect

As mentioned before a MOSFET is a four terminal device: gate, source, drain and bulk
(or substrate or body), so far we implicitly assumed that the source and the bulk are at the
same potential. The source – body junction always has to be reverse biased, hence usually
the bulk is connected to the most negative potential of the circuit for a n-MOSFET and to
the most positive for a p-MOSFET. For many transistors the source is not at the most
negative (or positive) potential of the entire circuit, for example, for cascode transistors in
amplifiers. The voltage drop between source and bulk, VSB, increases the depth of
depletion region in the substrate hence the depletion charge increases as well, this can be
accounted for by adding VSB as an additional term in eq.[21]:

QDMax = − 2qN A Si (2 F + VSB ) [27]

As VSB influences the depletion charge it will also influence the threshold voltage.
Therefore, the drain current is also a function of VSB hence sometimes the substrate is
referred to as a second gate.

Fig. 12: Diode connected MOSFET (a) showing the effect of the increasing V SB (body
effect) (b) (© Sze [2]).
Consider the circuit in fig. 12a, a so-called diode connected MOSFET which is used for
current mirrors. Since vDS = vGS the transistor is always in saturation. The vDS - √ID
characteristic in fig. 12b shows the influence of increasing source – body voltage
resulting in an increase of the threshold voltage. The equation for the threshold voltage
has to be modified using eq.[27]:

QSS 2qN A Si (2 F + VSB ) [28]

VT = GS − + + 2 F
COX COX
13
For simulation purposes this is often rewritten in the form (analogous to eq.[23]):

VT = VT 0 +  ( 2 F + VSB − 2 F )
QSS [29]
VT 0 = GS − + 2 F +  2 F
Cox
This is the equation used in SPICE for the level 1 MOSFET model.

Physical Channel Length

The source and drain n+ regions are usually created by diffusion which is not uni-
directional. Consequently, there will be some lateral diffusion under the gate during the
fabrication process. As a result, the actual physical channel length will be smaller than
the one drawn in the layout as illustrated in fig. 13.

Window etched in oxide

for n-diffusion Ldrawn

Cross-sectional view LD

Drain n+ Lph

Ldrawn
LD
Top view (layout)
Lph

Gate
Drain Source

Fig. 13: Difference between physical and drawn channel length.

In SPICE this is modelled by another parameter, the lateral diffusion LD. The physical
channel length Lph is then calculated as:

Lph = Ldrawn – 2LD [30]

which is used in the equations for the threshold voltage and the drain current.
(Note: Lph is often called the effective channel length in the literature, here the term
‘physical channel length’ was chosen to avoid confusion with the effective channel length
introduced for the channel length modulation.)

MOSFET Small Signal Characteristics in Saturation

The preceding large signal equations can now be used to derive an ac or small signal
model for a MOSFET in saturation. Initially we will consider the static or low frequency
case for which any capacitances can be neglected. Since the drain current is a function of

14
the gate - source and the source bulk voltage, two transconductance current sources are
required (in contrast to a bipolar transistor where only one is required).

The gate transconductance can be calculated by differentiating eq.[18]:

I D
= k ' (VGS − Vt )(1 + VDS )
W
gm =
VGS L
for VDS  1 [31]

gm = k '
W
(VGS − Vt ) = 2k ' W I D
L L

The simplifying approximation λVDS << 1 is often made for hand calculations.

Similarly, the body transconductance can be calculated:

I D V
= −k ' (VGS − Vt )(1 + VDS ) T
W
g mb = [32]
VSB L VSB

From eq.[29] we obtain:

VT 
=− = − [33]
VSB 2 2 F + VSB

which defines a factor χ which is equal to the rate of change of threshold voltage with
body bias voltage. Χ is also the ration gmb/gm; typical values are between 0.1 ..0.3 which
means that the gate-source voltage influences the drain current 3 – 10 times more than the
source-bulk voltage.

If the same approximation as for the gate transconductance is made that λVDS << 1, eq.
[32] simplifies to:

 k ' (W / L) I D
g mb = [34]
2(2F + VSB )

Finally, the output resistance ro can be calculated from eq.[17] and [18]
−1
 I  1
r0 =  D  = [35]
 VDS  I D

15
Above derivations allow us to form a first small-signal model for a MOSFET as shown in
fig. 14.

Fig. 14: Small signal, low-frequency MOSFET model.

It can be seen from the model that the input impedance is infinite and that if the source –
bulk voltage is zero, there is only one voltage controlled current source.

To derive a dynamic small signal model we have to include the varies capacitances
present in a MOSFET. Two types of capacitances can be distinguished: intrinsic and
extrinsic. Intrinsic capacitances are related to the electric field in the gate oxide which
also forms the channel. These capacitances are a function of the charge on the gate
electrode and in the channel & depletion region hence vary with the terminal voltages.
Extrinsic capacitances are caused by parasitic effects from the fabrication process and are
fixed.

Intrinsic Capacitance

Fig. 15a shows all intrinsic and extrinsic capacitances. The problem is how to distribute
the physical capacitances as shown in the cross-sectional view of the MOSFET (fig. 15a)
to the lumped capacitors used in a circuit model (fig. 15b). The lumped capacitor
comprise a range of intrinsic and extrinsic capacitances.

CGB

CGD CDB
G B
CGS
CSB
S
(a) (b)

Fig. 15: MOSFET capacitances. (a) shows the physical origin (© Allen and
Holberg [4]) and (b) the circuit diagram with lumped capacitances.

16
The physical origin of the intrinsic capacitances is the gate – semiconductor capacitor
with the gate oxide as dielectric (C2 in fig.15a) and the back-biased depletion regions that
exists between the source & bulk (CBS), drain & bulk (CBD) and channel & bulk (C4).
Capacitors C1 & C3 are extrinsic overlap capacitances and are fixed.

In triode region the channel is assumed of uniform depth and C2 is equally shared
between CGS and CGD. In the triode region C2 can easily be calculated:

C2 = WLCox. [36]

In saturation region the situation is more complicated. As the channel is pinched off near
the drain region, it can be shown that approximately 2/3 of the gate capacitance
contributes to CGS and nothing to CGD.

The depletion layer capacitances of the two reverse-biased p-n junctions formed between
the n+ source & drain regions and the bulk can be calculated by using the pn-junction
junction capacitance equation:

CSB0 CDB 0
CSB = and CDB = [37]
V V
1 + SB 1 + DB
V0 V0

where V0=0.6V .. 0.8V (built in voltage), CSB0 and CDB0 are the capacitance values at
zero junction bias and are usually extracted from measured data and are SPICE
parameters.

The gate capacitance (C2) is obviously in series with the channel depletion capacitance
(C4). The total capacitance is hence given by:

CoxCdepl
C gatetotal = [38]
Cox + Cdepl

Interestingly, the total gate capacitance depends on with what frequency it is measured. If
the ac signal used to measure the capacitance is of high frequency (>100 Hz) the change
in charge occurs at the edge of the depletion region and the charge in the channel is
constant (solid line). However, if the measurement frequency is lower than the
generation-recombination rate at the surface, the charge in the channel can follow the ac

Gate
Ctotal
COX Low frequency COX
VGS

Onset of strong inversion CDepl

CDepl = constant

High frequency

VT VGS
17
Fig. 16: The total gate capacitance depends on the measurement frequency.
signal and the total capacitance is Cox in the saturation region. Fig. 16 shows typical
curves for low and high frequency measurements.

Extrinsic Capacitance

Extrinsic capacitances are constant and are caused by overlaps of different regions (e.g.
C1 and C3 in fig. 15).
CGSO & CGDO in fig. 17a are constant overlap capacitances due to the lateral spread of the
source & drain diffusion regions beneath the gate. They fully contribute to CGD and CGS
in the lumped model in fig. 17b.
Gate

Source Drain
CGSO CGDO
n+ p n+

Fig. 17: Extrinsic capacitances due to the lateral diffusion of the

source/drain region into under the gate.

Another extrinsic capacitance, CGBO, originates from the constant overlap of the gate onto
the field oxide (which separates one transistor from the other). It is illustrated in fig. 18.
CGBO fully is attributed towards CGS and CGD, respectively.

Field oxide
CGBO CGBO

Fig. 18: Overlap capacitance originating from overlap of the gate onto
the field oxide.

Dynamic Small Signal MOSFET Model

With the above discussion we can now derive a small signal model for a MOSFET as
shown in fig. 19.

Fig. 19: Small signal model for a MOSFET in saturation. (© Gray and Meyer [3])

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Example:

Consider a n-channel MOSFET which is biased at ID=100A, VSB=2V and VDS=5V. The
following process and device parameters are specified:

ΦF=0.3V
W=30m; L=10m
γ=0.5V1/2
k’=16A/V2
λ=0.02V-1
tox=0.1m
CSBo=CDBo=0.1pF
CGSo=CGDo=0.01F
CGB=0.05pF

Derive the lumped components for the small signal model.

Transconductance:
W A
g m = 2k ' I D = 2 16  3 100 = 98S
L V
(assuming λVDS<<1)

Body transconductance:
 k ' (W / L) I D 16  3 100
g mb = = 0.5 = 15.2S
2 2 F + VSB 2  2.6

Output resistance:

ro = 1/(λID) = 1/(0.02∙100∙10-6) Ω = 500kΩ

Voltage from drain to body:

VDB = VDS + VSB =7V

Drain - bulk depletion capacitance:

CDB=CDB0/(1+VDB/V0)½ = 0.1pf/(1+7/0.6) ½ = 0.03pF

Source - bulk depletion capacitance:

CSB=CSB0/(1+VSB/V0)½ = 0.1pf/(1+2/0.6) ½ = 0.05pF

The intrinsic gate capacitance is (in saturation):

CGS,int=2/3WLCox = 2/3∙30∙10∙3.5∙10-4pF = 0.07pF

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Adding the overlap capacitances:

CGS = 0.07pF + 0.01pF = 0.08pF

The gate-drain capacitance consists only of overlap capacitance:

CGD = 0.01pF

Spice Level 1 Model

Fig. 20 shows the SPICE level 1 model used for transient analysis (a) and for ac analysis
(b). These particular diagrams are taken directly from the HSPICE manual [4]. The
model is based on the Schichman-Hodges Model [5] which was developed in the late
1960’s. It assumes long channels (>10m) and uniform doping profiles hence it is only
valid for devices that were state-of the art two decades ago. Because the model equations
are simple and easy to understand for circuit designers, it is still used for initial
simulations and mainly for hand calculations.

(a) (b)

Large signal model Small signal model

Fig. 20: SPICE level 1 model: (a) large signal or transient model, (b) small signal or ac model (© HSPICE
User’s Manual Vol. 2, [5])

A number of components have not been covered in the preceding sections which are:

The diodes in the large signal model are used to account for any leakage current into the
substrate. The equations used are:

(
ibd = I S e qvbd / kT − 1 )
(e − 1)
[39]
ibs = I S qvbs / kT

The source and drain resistors, rs and rd, are typically in the 50 - 100Ω range and are due
to the contact resistance. Usually, they do not have significant influence on the device
operation.

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In table 1 all parameters for the level one model are listed. Some of the parameters were
not covered in this course (MJ, CJSW, MJSW). They deal with the depletion capacitance
equations and take into account the doping profile of the source and drain regions.

SYMBOL PARAMETER DESCRIPTION

V TO VTO Zero bias threshold voltage
k' KP Transconductance parameter
λ LAMDA Channel length modulation
 GAMMA Body effect parameter
2ΦF PHI Surface inversion potential
t ox TOX Gate oxide thickness
NA NSUB Substrate doping concentration
LD LD Lateral diffusion
μ UO Surface mobility
IS IS S/B & D/B diode saturation current
V0 PB S/B & D/B diode built in voltage
CJ0 CJ S/B & D/B zero bias junction cap./m2
MJ MJ S/B & D/B doping profile grading coefficient
CJSW CJSW S/B & D/B zero bias perimeter doping grading coefficient
MJSW MSJW S/B & D/B perimeter doping grading coefficient
CGBO CGBO G/B overlap capacitance/m2
CGDO CGDO G/D overlap capacitance/m2
CGSO CGSO G/S overlap capacitance/m2
RD RD Drain series resistance
RS RS Source series resistance

Table 1: Parameters used for PSPICE level 1 model.

As reference the full equations for the level one model used in PSPICE are given below.

From PSPICE manuals (PSPRef.pdf, pp. 198):

Drain current equations
Normal mode: Vds > 0
Case 1
for cutoff region: Vgs-V to < 0
then: Idrain = 0
Case 2
for linear region: Vds < Vgs-V to
then: Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·Vds·(2·(Vgs-V to )-Vds)
Case 3
for saturation region: 0 < Vgs-V to < Vds
then: Idrain = (W/L)·(KP/2)·(1+LAMBDA·Vds)·(Vgs-V to ) 2
where
V to = VTO+GAMMA·((PHI-Vbs)1/2 -PHI 1/2)
Inverted mode: Vds < 0
Switch the source and drain in the normal mode equations above.

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Capacitance Equations

Cbs = bulk-source capacitance = area cap. + sidewall cap. + transit time cap.
Cbd = bulk-drain capacitance = area cap. + sidewall cap. + transit time cap.
where
if
CBS = 0 AND CBD = 0
then
Cbs = AS·CJ·Cbsj + PS·CJSW·Cbss + TT·Gbs
Cbd = AD·CJ·Cbdj + PD·CJSW·Cbds + TT·Gds
else
Cbs = CBS·Cbsj + PS·CJSW·Cbss + TT·Gbs
Cbd = CBD·Cbdj + PD·CJSW·Cbds + TT·Gds
where
Gbs = DC bulk-source conductance = dIbs/dVbs
Gbd = DC bulk-drain conductance = dIbd/dVbd
if
Vbs < FC·PB
then
Cbsj = (1-Vbs/PB)-MJ
Cbss = (1-Vbs/PBSW)-MJSW
if
Vbs > FC·PB
then
Cbsj = (1-FC)-(1+MJ)·(1-FC·(1+MJ)+MJ·Vbs/PB)
Cbss = (1-FC)-(1+MJSW)·(1-FC·(1+MJSW)+MJSW·Vbs/PBSW)
if
Vbd < FC·PB
then
Cbdj = (1-Vbd/PB)-MJ
Cbds = (1-Vbd/PBSW)-MJSW
if
Vbd > FC·PB
then
Cbdj = (1-FC)-(1+MJ)·(1-FC·(1+MJ)+MJ·Vbd/PB)
Cbds = (1-FC)-(1+MJSW)·(1-FC·(1+MJSW))
Cgs = gate-source overlap capacitance = CGSO·W
Cgd = gate-drain overlap capacitance = CGDO·W
Cgb = gate-bulk overlap capacitance = CGBO·L

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