MOSFET

+ MOSFET stands for Metal Oxide Silicon Field Effect Transistor or Metal Oxide Semiconductor Field
Effect Transistor. This is also called as IGFET meaning Insulated Gate Field Effect Transistor.
+ The MOSFET, different from the JFET, has no pn junction structure; instead, the gate of the MOSFET is
insulated from the channel by a silicon dioxide (SiO 2) layer.
+ The two basic types of MOSFETs are enhancement (E) and depletion (D). Of the two types, the
enhancement MOSFET is more widely used.
+ The voltage at gate controls the operation of the MOSFET. In this case, both positive and negative
voltages can be applied on the gate as it is insulated from the channel.
+ With negative gate bias voltage, it acts as depletion MOSFET while with positive gate bias voltage it acts
as an Enhancement MOSFET.
E-MOSFET
+ The basic construction of the n -channel enhancement-type MOSFET is provided above.
+ A slab of p -type material is formed from a silicon base and is referred to as the substrate.
+ The substrate is sometimes internally connected to the source terminal, whereas in other cases
a fourth lead (labeled SS) is made available for external control of its potential level.
+ The source and drain terminals are connected through metallic contacts to n -doped regions.
+ The primary difference between the construction of depletion-type and enhancement-type
MOSFETs—the absence of a channel as a constructed component of the device.
+ The SiO2 layer is present to isolate the gate metallic platform from the region between the
drain and source.
Operation

+ If VGS is set at 0 V and a voltage applied between the drain and the source, the absence of an n -channel will result in a current of
effectively 0 A
+ It is not sufficient to have a large accumulation of carriers (electrons) at the drain and the source (due to the n -doped regions) if a
path fails to exist between the two
+ With VDS some positive voltage, VGS at 0 V, and terminal SS directly connected to the source, there are in fact two reverse-
biased p – n junctions between the n -doped regions and the p -substrate to oppose any significant flow between drain and source
+ In the below Fig, both VDS and VGS have been set at some positive voltage greater than 0 V
+ The positive potential at the gate will pressure the holes (since like charges repel) in the p -substrate along the edge of the SiO 2
layer to leave the area and enter deeper regions of the p -substrate, as shown in the figure
+ The result is a depletion region near the SiO 2 insulating layer void of holes. However, the electrons in the p -substrate (the
minority carriers of the material) will be attracted to the positive gate and accumulate in the region near the surface of the SiO 2
layer.
+ As VGS increases in magnitude, the concentration of electrons near the SiO 2 surface increases until
eventually the induced n -type region can support a measurable flow between drain and source
+ The level of VGS that results in the significant increase in drain current is called the threshold voltage and
is given the symbol VT
+ Since the channel is nonexistent with V GS = 0 V and “enhanced” by the application of a positive gate-to-
source voltage, this type of MOSFET is called an enhancement-type MOSFET
+ As VGS is increased beyond the threshold level, the density of free carriers in the induced channel will
increase, resulting in an increased level of drain current
+ However, if VGS is constant and the level of VDS increases , the drain current will eventually reach a
saturation level
+ The leveling off of ID is due to a pinching-off process depicted by the narrower channel at the drain end
of the induced channel shown in the above figure
+ The reduction in gate-to-drain voltage will in turn reduce the attractive forces for free carriers (electrons)
in this region of the induced channel, causing a reduction in the effective channel width. Eventually, the
channel will be reduced to the point of pinch-off and a saturation condition will be established
Characteristics
+ For a fixed value of V T , the higher the level of VGS , the greater is the saturation level for
VDS , as shown in the above figure by the locus of saturation levels
+ For values of VGS less than the threshold level, the drain current of an enhancement type
MOSFET is 0 mA.
+ For levels of VGS ˃ VT, the drain current is related to the applied gate-to-source voltage by
the following nonlinear relationship:
D-MOSFET

+ A slab of p -type material is formed from a silicon base and is referred to as the substrate.
+ In some cases, the substrate is internally connected to the source terminal.
+ The source and drain terminals are connected through metallic contacts to n -doped regions
linked by an n -channel as shown in the below figure.
+ The gate is also connected to a metal contact surface but remains insulated from the n -channel
by a very thin silicon dioxide (SiO2) layer.
+ There is no direct electrical connection between the gate terminal and the channel of a MOSFET.
+ It is the insulating layer of SiO2 in the MOSFET construction that accounts for the very
desirable high input impedance of the device.
Operation & Characteristics
Operation & Characteristics

+ The gate-to-source voltage is set to 0 V by the direct connection from one terminal to the
other, and a voltage VDD is applied to drain to source terminals.
+ The result is an attraction of the free electrons of the n-channel for the positive voltage at the
drain.
+ The resulting current with VGS = 0 V continues to be labeled IDSS
Operation & Characteristics
Operation & Characteristics
Operation & Characteristics

+ VGS is set at a negative voltage such as -1 V. The negative potential at the gate will tend to pressure
electrons toward the p -type substrate (like charges repel) and attract holes from the p -type substrate
(opposite charges attract) in the above figure.
+ The more negative the bias, the higher is the rate of recombination. The resulting level of drain current is
therefore reduced with increasing negative bias for V GS
+ For positive values of VGS , the positive gate will draw additional electrons (free carriers) from the p -
type substrate due to the reverse leakage current and establish new carriers through the collisions
resulting between accelerating particles.
+ As the gate-to-source voltage continues to increase in the positive direction, characteristics curve reveals
that the drain current will increase at a rapid rate
EMOS Biasing
(Voltage Divider Bias)
Problem-1

+ Determine VGS and VDS for the E-MOSFET circuit in the attached Figure. Assume this particular
MOSFET has minimum values of ID(on) = 200 mA at VGS = 4 V and VGS(th) = 2 V.
DMOS Bias
Problem-2

+ Determine the drain-to-source voltage in the circuit of attached figure. The

MOSFET datasheet gives VGS(off) = -8 V and IDSS = 12 mA.
EMOS ac model
CMOS

+ A very effective logic circuit can be established by constructing a p -channel and an n -channel
MOSFET on the same substrate
+ The configuration is referred to as a complementary MOSFET arrangement (CMOS)
+ It has extensive applications in computer logic design. The relatively high input impedance, fast
switching speeds, and lower operating power levels of the CMOS configuration have resulted in a whole
new discipline referred to as CMOS logic design
MOS Current Mirror

The current mirror circuits are simple current sources which gives
constant current. The current mirror circuits are based on the principle
that, if the gate to source voltage of two identical MOSFETs are equal
then the drain current flowing through them is equal.
BJT Current Mirror

+ An often-used circuit applying the bipolar junction transistor is the current mirror,
which serves as a simple current regulator, supplying nearly constant current to a
load over a wide range of load resistances.
+ The function of the current mirror circuit: to regulate current through the load
resistor by conveniently adjusting the value of Rbias.