ECS-Components

Chapter 4
Components for Electronic Systems
• Description of geometrical, thermal and some electrical

properties of main types of components. No description
of electrical properties of monolithic circuits.
The course material was developed in INSIGTH II, a project sponsored by

the Leonardo da Vinci program of the European Union
Electronic Pack….. Chapter 4
Components for Electronic Systems Slide 1
Hole Mounted Resistors
• Mature design, fig. 4.1:
–Carbon composite (a)
–Metal film (b)
–Wire wound (c)

Surface Mounted Resistors
• Fig.4.2.a: Thick film layers on ceramic
substrate, rectangular shape

Fig. 4.2 b): Metal system for termination on SMD resistors.

Fig. 4.2 c): MELF-resistors have cylindrical body.

(MELF is acronym for Metal Electrode Face Bonding)
Table 4.1. Properties of SMD resistors (Philips).
Resistance range and tolerance 10 ohm to 1 Mohm (E24* series) ± 2%
• Table 4.1: Properties of SMD resistors 1 ohm to 10 Mohm (E24 series) ± 5%
1 ohm to 10 Mohm (E12 series) ±10%
Dimensions 3,2 x 1,6 x 0,6 mm
Operating temperature range -55°C to + 155°C
Temperature coefficient (-40°C to 125°C) <+200 x 10-6/K
Absolute max. dissipation at Tamb= 70°C 0,25 W
Maximum permissible voltage 200 V (r.m.s.)
Climatic category (IEC68) 55/155/56
Jumper resistance = 50 mohm
Maximum current 2A
*See Table 4.2

Table. 4.2: The resistance series E24, E12 and E6. The numbers mean that for
example in series E6 there are 6 resistance values for each decade: 10,
• Table 4.2: The resistance series E24,
15, 22, 33, 47 and 68 x10n ohms.
E24 12
10 11and 6 16 18 20 22 24 27 30 33 36 39 43 47 51 56 62 68 75 82 91
12 13 15
E12 10 12 15 18 22 27 33 39 47 56 68 82
E6 10 15 22 33 47 68

Capacitors
• In addition the capacitance, the following properties
are important:
• Maximum voltage rating
• Temperature dependence of the capacitance
(temperature coefficient)
• Loss tangent (tan δ), see below
• Equivalent series resistance
• Long term stability and ageing phenomena
• High frequency properties
• Leakage current
• Ability to withstand various production processes (high
temperature, etc.)
• Price, physical size, etc.

Capacitors, continued
• Electrical model:
C = (o r • A) /d
• Fig. 4.3: Electrical

equivalent model for Rp
capacitor. If Rp can be L
Rs
neglected the impedance is C
given by:
| Z | = [ Rs2 + (ωL - 1/ ωC)2]1/2
Rs = series resistance (Rp neglected),

L = inductance

• Fig. 4.4: The frequency
dependence of impedance for
multilayer ceramic capacitors
(below) and tantalum
electrolytic capacitors (top), all
having 100 nF capacitance
value.
Zmin at frequency where:
L = 1/C

Fig. 4.5: Frequency dependence of the loss tangent tan  schematically.
tan  = R / |Im Z | = [Rp + Rs ( 1+ ( CRp)2) ] / ( CRp2 - L (1+ ( CRp)2) ]

• Main types:
– Ceramic multilayer
– Electrolytic dry, polarized
– Electrolytic, wet, polarized
– Metallized plastic film
– Mica http://en.wikipedia.org/wiki/Capacitors
SMD ceramic at top left
SMD tantalum at bottom left
through-hole tantalum at top right
through-hole electrolytic at bottom right
http://en.wikipedia.org/wiki/Capacitors
Various Capacitors.
The large cylinders are high value
electrolytic types

• Multilayer Ceramic Capacitors
Fig. 4.7.a: SMD Multilayer Ceramic Capacitor
Fig. 4.7.b: Metal system for the end

termination of multilayer ceramic
capacitors.

Multilayer Ceramic
Capacitor, continued
• Class 1: Low
capacitance, good
electrical properties,
types NP0, N220, N750,
COG, etc.
• Class 2: High
capacitance, poorer
electrical behaviour,
types X7R, Z5U
Fig. 4.8: Relative dielectric constant for ferroelectric ceramic

compositions (class 2), as a function of temperature, near the Curie
point
Multilayer Ceramic
Fig. 4.9: Properties
of dielectrics of the
types NP0, X7R and
Z5U in SMD
ceramic multilayer
capacitors.
Top: The voltage

dependence of
capacitance.
Middle: Loss tangent

as function of
temperature.
Bottom: The
temperature
coefficient of the
capacitance
(Philips).
Multilayer Ceramic Capacitors, continued
Fig. 4.10: Crack formation because of thermal stress

in ceramic capacitors
• Tantalum, Dry Electrolytic
– Very high capacitance, low voltages, low leakage current
http://www.nec-tokin.com
• Electrolytic Capacitors – why they are polarised:

– The capacitance is the oxidised surface of the anode
– Reversed polarity will remove the oxide by reduxtion reaction

• Tantalum, Dry Electrolytic
Dissipation factors vary with temperature: Maximum values which are not exceeded by any capacitor
are as follows.
Temperature -55 C 25 C 85 C 125 C

Rated Voltage 4 to 10 V d.c. 10% 12% 12% 12%
Rated Voltage 15 to 50 V d.c. 8% 6% 6% 6%
The d.c. leakage current (at rated voltage) is within the limit set below
25 C < 0,01 µA/µF V or < 1 µA whichever is greater

85 C < 0,10 µA/µF V or < 10 µA whichever is greater
125 C < 0,125 µA/µF V or < 12,5 µA whichever is greater
Fig. 4.11 b): Electrical properties of dry tantalum electrolytic capacitors.

(Data from Philips)

Wet Electrolytic Aluminium Capacitors
Fig. 4.12 a): Aluminium electrolytic capacitor for SMD

mounting. (From Philips)
Wet Electrolytic Aluminium Capacitors
Fig. 4.12 b):
Aluminium electrolytic
capacitor properties
(Philips).
Top: Temperature
dependence of the
capacitance, relative to
the value at 20 °C.
Middle: Temperature
dependence of tan 
Bottom: Temperature
dependence of
impedance at a
frequency of 10 kHz.
Diodes and Transistors
Fig. 4.13: Axial, plastic encapsulated, hole mounted diodes to the left.
Centre: A plastic can with metal base for power diodes. It can be hole mounted
or surface mounted, depending on how the leads are bent. The base is screwed
to the substrate.
Right: A higher power diode in a metal can. Screw mounted to the substrate for
efficient thermal contact.

Diodes and Transistors, continued
Fig. 4.14: Various types of hole mounted transistor packages:

a) Left: Plastic packages,
b) Centre: Low power metal packages
c) Right: Metal package for high power transistors. For the
high power package, the collector is connected to the metal
body.
Diodes and Transistors , continued
Fig. 4.15: MELF-package for SMD diodes. The standard size is

designated SOD-80, with dimensions shown to the right.
(MELF: Metal Electrode Face Bonding)

Diodes and Transistors, continued
Fig. 4.16: SOT-packages for SMD diodes and transistors: The most common,
SOT-23 top left, SOT-89 for power transistors in the middle, and SOT-143 with
four terminals to the right. The dimensions for SOT-23 are shown bottom left, and
a cut-through SOT-89 in the middle. Ceramic SMD transistor packages with
terminal placement like for SOT-23 are shown bottom right.
IC Packages
• Plastic or Ceramic IC Packages?
• Plastic:
– Not hermetic
– Low price in large quantities
– High initial cost
– Low thermal conductivity
– Limited time at high temperature
– Thermal mismatch to Si chip and metals
– Not suitable for for high frequency circuits
• Ceramic:
– Hermetic, good reliability
– Costly, but OK for prototyping
– Good thermal conductivity
– Low thermal coefficient of expansion, matches well with Si, mismatch
to organic substrates
– Gold metallization must be removed
– Well defined high frequency properties

Packages for Hole Mounted ICs
Fig. 4.17:a) DIP (Dual-in-line) IC package. b) Partly cross-

sectioned DIP package which shows the silicon chip, bonding
wires, lead frame and plastic body. c) The terminal organisation
for 4 two-input NOR gates in a 14 pins package.
Packages for Hole Mounted ICs,
continued
Fig. 4.18: Pin grid packages: To the left a cavity up ceramic

package, and to the right a plastic moulded package.
SMD IC Packages
• Small Outline (SO)

• Plastic Leaded Chip Carrier (PLCC)
• Leadless Chip Carrier (LLCC)
• Leaded Ceramic Chip Carrier (LDCC)
• Flatpack, mini-flatpack
• TapePak
• Chip Scale Packages

SMD IC Packages, continued
Fig. 4.19: Surface mounted SO (Small Outline) IC package.

(From Philips)
SMD IC Packages, continued
Outline Encapsulation Maximum width
SO Maximum width Maximum length Lead end to lead end
[mm] [mm] [mm]
SO-8 4,0 5,00 6,2
SO-8 7,6 7,6 12,4
SO-14 4,0 8,75 6,2
SO-16 4,0 10,00 6,2
SO-16L 7,6 10,5 10,65
SO-20 7,6 13,0 10,65
SO-24 7,6 15,6 10,65
SO-28 7,6 18,1 10,65
VLO-40 7,6 15,5 12,8
VSO-56 11,1 21,6 15,8
Table 4.3: Dimensions for SO- and VSO packages. Centre-to-

centre lead distance is normally 50 mils, except for VSO-40
with 30 mils and VSO-56 with 0.75 mm.
SMD IC Packages:
Plastic Leaded Chip Carrier (PLCC)
Fig. 4.20: Plastic leaded chip carrier with (PLCC). They are normally
square with an equal number of terminals on all four sides (top). For
large DRAMs, the package has terminals on only two sides, also being
called SOJ. The bottom figure shows a 1 or 4 Mbit DRAM package.
SMD IC Packages:
Plastic Leaded Chip Carrier (PLCC)
Leads Format Lead pitch Maximum body Maximum Device Typical
dimensions [AxB] Dimensions (LxW) Height (C)
[mm] [mm] [mm] [mm]
20 5x5 1,27 9,1x9,1 10,1x10,1 3,5-4,7
28 7x7 1,27 11,6x11,6 12,6x12,6 3,5-4,7
44 11x11 1,27 16,8x16,8 17,8x17,8 3,5-4,7
52 13x13 1,27 19,3x19,3 20,3x20,3 3,5-4,7
68 17x17 1,27 24,4x24,4 25,4x25,4 3,5-4,7
18 5x4 1,27 10,9x7,5 11,9x8,5 3,5-4,7
28 9x5 1,27 14,1x9,0 15,1x10,0 3,5-4,7
32 9x7 1,27 14,1x11,6 15,1x12,6 3,5-4,7
Table 4.4: Dimensions for PLCC packages. Format means

the number of terminals on two neighbouring sides.

Leadless Chip Carrier (LLCC)
Leaded Ceramic Chip Carrier (LDCC)
Fig. 4.21 a): The various types of ceramic chip carriers [4.15].
Types A -D to the left are leadless (LLCC), whereas types A
and B to the right are meant for mounting leads (LDCC).

Leadless Chip Carrier (LLCC)
Fig. 4.21 b): LLCC packages, additional details. The longest

terminal is to designate electrical terminal number 1 in the circuit.

Leadless Chip Carrier (LLCC),
continued
Leads Format Pad Pitch (p) Maximum Dimension (AxB)

[mm] [mm]
20 5x5 1,27 9,1x9,1
28 7x7 1,27 11,6x11,6
44 11x11 1,27 16,8x16,8
52 13x13 1,27 19,3x19,3
68 17x17 1,27 24,4x24,4
84 21x21 1,27 29,6x29,6
18 5x4 1,27 10,9x7,5
28 9x5 1,27 14,1x9,0
32 9x7 1,27 14,1x11,6
Table 4.5. LLCCs, dimensions.

Leaded Ceramic Chip Carrier
(LDCC)
Fig. 4.22: Leaded ceramic chip carriers.

Leaded Ceramic Chip Carrier
(LDCC), continued
Fig. 4.23: Various shapes of the leads, and leadless termination for
comparison.

Flatpacks
Fig. 4.24: Quad flatpack with leads on all four sides.

Flatpacks are usually made of plastic or ceramic. They have
leads on four or two sides.
Mini-flatpacks
Fig. 4.25: Mini-flatpacks is a name for higher density

flatpacks: Typically 84 - 244 terminals and a pitch of 25 mils.
TapePak
Fig. 4.26: National Semiconductor´s TapePak component packages are

specified with terminal numbers between 40 and close to 600. To the left
we see a 40 leads TapePak in the form it is received by the user with a
protective ring around it, and test points outside the ring. To the right is
TapePak 40 after excising and lead bending, seen from above and from
the side.
High Performance Packages
• Multilayer ceramic, Al2O3 or AlN

– Ground planes
– Controlled characteristic impedance
– Thermal vias

Fig. 4.27: Thermal via-holes in the printed circuit board, for

better heat conduction.

Fig. 4.28: Multilayer package for high frequency GaAs circuits with 3
ground planes, 2 voltage planes, 1 signal layer and a top conductor layer
for contacts and sealing (Triquint).
High Performance Packages,
continued
Fig. 4.29: Multichip package for memory module in a Hitachi

high-performance computer [4.18]. The module contains 6
ECL chips, mounted by flip chip.
Packages: Future Trends
Fig. 4.30: Comparison between the size of various package

forms for an integrated circuit with approximately 64
terminals.
Packages: Future Trends, continued
Fig. 4.31: History and prognosis for the use of various sizes of
passive SMD components, in percentage of the total number.

Metallization of Terminals
• Passives
– Ag in alloy with Pd, Ni barrier, Sn/Pb
– Ag in solder alloy
– With adhesive mounting:
• No Sn/Pb on terminal
• ICs
– Au removed
– Sn/Pb coating

Terminal Metallisation,
Solderability and Reliability
Fig. 4.32: Strain at fracture of solder fillet as function of gold

concentration in the solder metal, relative to value without gold.
Electrostatic Discharges (ESD)
• Unprotected MOS: Max 5 - 80 V on input

before destroyed
• Triboelectricity: >>1000 V discharge
• Billions of $ damage annually
• Protected circuits tolerate 500 - 8000 V
• Extensive precautions in industry, handling
and packing

Electrostatic Discharges - Component
Damages and Precautions
Fig. 4.33: MOS transistor schematically. The gate oxide is

very vulnerable for damage by electrostatic discharge. Gate
oxides down below 200 Å (20 nm) are now used.
Damages and Precautions, continued
Fig. 4.34: CMOS circuit exposed to electrostatic damage: Silicon

has molten in a small area. Picture size  5m x 5m.
Damages and Precautions, continued
Fig. 4.35: ESD protection circuit at in- and outputs for MOS and for bipolar
circuits.

Component Packaging
• Paper tape (hole mounted passives)
• Blister tape (SMD passives, discretes, small
ICs)
• Sticks (DIPs, SMD ICs)
• Waffle trays (Flatpacks)
• Stack magazine
• Bulk: Not suited for automatic mounting

Component Packaging
for Automatic Placement
Fig. 4.36: Blister tape for surface mounted components. Standard

dimensions for 8 mm wide tape.
Component Packaging
Fig. 4.37: Plastic sticks as packaging for SMD integrated circuits.

Component Packaging
Fig. 4.38: Waffle trays packaging for flatpacks to the left, frame for
stacking of single component to the right.

Chapter 4
Components for Electronic Systems
End of overhead series from Chapter 4


ECS-Components

Uploaded by

Document Information

Original Description:

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

ECS-Components

Uploaded by

Copyright:

Available Formats

Chapter 4

Components for Electronic Systems

• Description of geometrical, thermal and some electrical

The course material was developed in INSIGTH II, a project sponsored by

Electronic Pack….. Chapter 4

Electronic Pack….. Chapter 4

Fig. 4.2 b): Metal system for termination on SMD resistors.

Electronic Pack….. Chapter 4

Fig. 4.2 c): MELF-resistors have cylindrical body.

Electronic Pack….. Chapter 4

Electronic Pack….. Chapter 4

Electronic Pack….. Chapter 4

• Fig. 4.3: Electrical

| Z | = [ Rs2 + (ωL - 1/ ωC)2]1/2

Rs = series resistance (Rp neglected),

Electronic Pack….. Chapter 4

Zmin at frequency where:

Electronic Pack….. Chapter 4

Fig. 4.5: Frequency dependence of the loss tangent tan  schematically.

tan  = R / |Im Z | = [Rp + Rs ( 1+ ( CRp)2) ] / ( CRp2 - L (1+ ( CRp)2) ]

Electronic Pack….. Chapter 4

Fig. 4.7.a: SMD Multilayer Ceramic Capacitor

Fig. 4.7.b: Metal system for the end

Electronic Pack….. Chapter 4

Fig. 4.8: Relative dielectric constant for ferroelectric ceramic

Top: The voltage

Middle: Loss tangent

Fig. 4.10: Crack formation because of thermal stress

• Electrolytic Capacitors – why they are polarised:

Electronic Pack….. Chapter 4

Temperature -55 C 25 C 85 C 125 C

25 C < 0,01 µA/µF V or < 1 µA whichever is greater

Fig. 4.11 b): Electrical properties of dry tantalum electrolytic capacitors.

Electronic Pack….. Chapter 4

Fig. 4.12 a): Aluminium electrolytic capacitor for SMD

Electronic Pack….. Chapter 4

Fig. 4.14: Various types of hole mounted transistor packages:

Fig. 4.15: MELF-package for SMD diodes. The standard size is

Electronic Pack….. Chapter 4

Electronic Pack….. Chapter 4

Fig. 4.17:a) DIP (Dual-in-line) IC package. b) Partly cross-

Fig. 4.18: Pin grid packages: To the left a cavity up ceramic

• Small Outline (SO)

Electronic Pack….. Chapter 4

Fig. 4.19: Surface mounted SO (Small Outline) IC package.

Table 4.3: Dimensions for SO- and VSO packages. Centre-to-

Table 4.4: Dimensions for PLCC packages. Format means

Electronic Pack….. Chapter 4

Electronic Pack….. Chapter 4

Fig. 4.21 b): LLCC packages, additional details. The longest

Electronic Pack….. Chapter 4

Leads Format Pad Pitch (p) Maximum Dimension (AxB)

Table 4.5. LLCCs, dimensions.

Electronic Pack….. Chapter 4

Fig. 4.22: Leaded ceramic chip carriers.

Electronic Pack….. Chapter 4

Fig. 4.24: Quad flatpack with leads on all four sides.

Fig. 4.25: Mini-flatpacks is a name for higher density

Fig. 4.26: National Semiconductor´s TapePak component packages are

• Multilayer ceramic, Al2O3 or AlN

Electronic Pack….. Chapter 4

Fig. 4.27: Thermal via-holes in the printed circuit board, for