EEE/ INSTR F313

Analog Digital VLSI Design

BITS Pilani
Pilani Campus Anu Gupta
Analog Digital VLSI Design

layouts, design rules, mismatch

Organisation

Design rules, Schematic to layout, vice versa,

Big layouts, Minimize Parasitics

Matched components

 Over-etching errors

unit components design

design using non unit component

 Boundary condition matching

Common centroid layout, parasitic cap estimation

BITS Pilani, Pilani Campus

MOSFET layout—top view

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Minimum layer width / spacing
rule

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design Rules contd…

• Scalable design rules-----same set can be

used for next tech generation by changing
λ. Worst case values of spacings, widths
etc. are used , so can’t be an optimized
set. e. g. MOSIS design rules

• Absolute design rules----optimized set but

same set can’t be used for next tech gen.
Entire new set is to be created.
Non scalable design rules -example

• Width of power rails (Vdd/ Gnd)--- increases in scaled down technology

• Reason--- due to miniaturization, more devices are available in same Si

area.

• So more circuits are created to get more functions.

• Hence Vdd rail has to supply power to increased no. of circuits.

• So current supplied by Vdd rail increases.

• If dimensions of Vdd rail is reduced, it will increase the current density

along the length of wire.

• This causes a very heavy electrical stress leading to electromigration

phenomena

BITS Pilani, Pilani Campus

Electro-migration
• Electromigration is the gradual displacement of metal atoms in a
semiconductor.

• It occurs when the current density is high enough to cause the drift
of metal (Al)/ Cu) ions in the direction of the electron flow, and is
characterized by the ion flux density.

BITS Pilani, Pilani Campus

Prevention of electromigration
• This density depends on the magnitude of forces that tend to hold
the ions in place, i.e., the nature of the conductor, crystal size,
interface and grain-boundary chemistry, and the magnitude of forces
that tend to dislodge them, including the current density,
temperature and mechanical stresses.

• It can be prevented by –

1. Widen the wire to reduce current density.

2. Lower the supply voltage.

BITS Pilani, Pilani Campus

 BITS Pilani
Pilani Campus

Stick diagram and layout of a circuit

CMOS inverter schematic

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CIRCUIT AND LAYOUT

Try more examples

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CMOS inverter stick diagram

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CMOS inverter layout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

TANNER EDA TOOL
4 NAND GATES
CADENCE
Full adder design/ layout
Other layouts of MOSFET

Annular transistor

Elongated annular
transistor
Dense MOS layouts

metal1

metal2

Waffle transistor Bent transistor

Compute w/L?
 BITS Pilani
Pilani Campus

Minimization of Si area in layout--

Eulers path approach
Layout of complex gates- Reducing area using
EULERS path- minimize diffusion breaks
• Ordering of inputs
• Minimize diffusion breaks by identifying common Eulers path
Random Ordering of the polysilicon gate columns.
Eulers path Ordering of the polysilicon gate columns.
 BITS Pilani
Pilani Campus

Asymmetry in source drain region

Shadowing effect
Layout to mitigate Shadowing effect
Chapter-18, Razavi

Preferred layout to 

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Parasitic minimization in layout

MOS LAYOUT

Total Si Area‐‐ 80 λ x 12λ= 960 λ2

λ
λ 2λ
2λ

5λ
Total capacitance ----AREA CAP. + FRINGING CAP .

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Junction cap-single transistor
How to reduce parasitic
capacitances?
Careful layout by junction sharing
Application of technique
 Total  drain Si Area‐‐
2(20 λ x 6λ)= 120 λ2
Perimeter‐‐‐ 24 λ

20λ 6λ Total  source  Si Area‐‐
6λ 6λ
2(20 λ x 5λ) +(20 λ x 6λ) =
320 λ2

Perimeter‐‐‐
5λ 5λ (30+30+12) λ
=72  λ
Fingered layout—source region,
2 λ= 0.5 um
View of fingered layout
Optimum no. of fingers– to
minimize perimeter capacitance.
3 fingers  4 fingers 

Note--- in this example, perimeter of side facing channel is not ignored.

Students should try this example again by ignoring that side perimeter.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Rule---Min. S/D perimeter
capacitance for odd no. of fingers N

For min. S/D capacitance‐‐‐

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Parallel plate Capacitor

Parallel plate capacitor---Cpp
Parallel plate capacitor---Cpp
Total capacitance Cpp ----AREA CAP. + FRINGING CAP .

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Effect of dimensions— pronounced
fringing effect
Cpp ---capacitance estimation formula
Yuan & Tricks ---
more accurate formula
2 level metallization
Cpp---single/ Multilevel layers—fringing effect
Interaction with Multi level
layers

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

CAPACITOR LAYOUTS
RESISTOR LAYOUT
Big Resistor
RESISTOR LAYOUT
 BITS Pilani
Pilani Campus

Matching of Components
Matching of Components

• Remove Over etching error---Large device => many

small unit devices

• Achieve Uniform rate of reaction----Same boundary

conditions/ environment around devices
Diff pair layout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Matched diff. pair layout—
Large (W/L)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Layout technique---Add dummy

components
What if unit devices change randomly?

Since one device is facing larger change in dimension,

maintaining constant ratio would be difficult.

So, We should have same change in all unit devices. how?

Inter-digitization
Matched diff. pair layout—
add dummy transistor

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Layout technique—keep ratio

constant by using multiple unit components
 Overetching / under cutting –MOS
dimensions
L
Poly layer

∆e

w
Over etched Poly layer

• (W/L)u = 8um/2um= 4 desired

• After over etching ---

• (W/L)u = 7um/1um= 7; 0.5um= ∆e
Absolute dimension–will change
Remedy---keep ratio constant-----

• strategy-- use Unit components w=L

• Unit transistors/ cap./ resistor ----
• (X/Y)u = 10um/10um, RATIO=1

• After fab. (X/Y)u  9um/9um, RATIO=1

• Conclusion— Abs. dimensions change,

ratio does not change
Ratio of Matched devices
• (W/L)1 = 2, (W/L)2 = 8, ratio= 4
L is same in all trans.

• We take unit transistor(W)u = 10um

• After fab. (W)u  9um

(W)2 = 8(W)u =4
(W)1 2(W)u

Thus, ratio remains same, if same unit device is

used
Using multiple units to create larger device
Matched diff. pair layout—
Large (W/L)—2 gate fingers in each

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Gradient effect on matching

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 BITS Pilani
Pilani Campus

Layout technique---
minimize Gradient effect on matching
Common centroid layout
Inter-digitization

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Common centroid layout

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

D D D

S
S S
Process gradient-----1% change in width

A=4.06
B= 4.22

1            1.01    1.02    1.03       1.04       1.05    1.06    1.07   

A=4.14
matching
B= 4.14
1            1.01    1.02    1.03       1.04       1.05    1.06    1.07   

A=4.12
B= 4.16

1            1.01    1.02    1.03       1.04       1.05    1.06    1.07   
Reduce mismatches
Bulk (backgate contact)
Over-Etching
BIG RESISTOR (unit components)
 BITS Pilani
Pilani Campus

END
BITS Pilani
Pilani Campus
BITS Pilani
Pilani Campus
 BITS Pilani
Pilani Campus

NON SQUARE UNIT COMPONENT

• Let
• C1/ C2 = 3.4 = 2+1.4
• = [6/3] + [1.4/1]
• [6/3]---can be implemented by using unit
capacitors
• [1.4/1]---we require non unit capacitor
• Mismatch can occur due to second term
No mismatch condition
• We should design non unit cap. Such that
ratio (1.4) remains constant/ minimum
even after overetching
• How to design?
• What is the condition?
Condition

= c1
c2

εr1= εr2
Non unit sized cap

= 1.4
 BITS Pilani
Pilani Campus

LATCH UP
latchup

Parasitic bipolars: a vertical PNP device formed by the P+/N well/P Substrate junctions,
and a horizontal NPN device formed by the lateral N+ / P substrate / N well junctions.
Several design ways to reduce the
possibility of latchup:
1.Reduce the beta of either or both parasitic
devices. In practice this can be achieved by
increasing the spacing between the devices,

2 Increase well and substrate doping

concentrations to reduce Rwell and Rsub.
For example using retrograde doped wells.

3 Provide alternative (or better) collectors

of the minority carriers. For example the
use of guard rings around devices.

4 In fabrication use SOI (silicon on

Insulator / SIMOX MOSFET
SOI MOSFET