MOS
Field
Effect
Transistors


(MOSFETs)


Electronics
2.

DE
TTK


Sedra/Smith

Microelectronic
Circuits


Chapter
4



DE
TTK
 1

4.
Chapter
 
 
 
 
 
Contents


1.  
 Device
structure
and
Physical
OperaEon

2.  
 Current
Voltage
CharacterisEcs

3.  
 MOSFET
Circuits
at
DC

4.  
 MOSFET
as
an
Amplifier
and
as
a
Switch

5.  
 Biasing
in
MOS
Amplifiers

6.  
 Small‐Signal
OperaEon
and
Models

7.  
 Single
Stage
MOS
Amplifiers

8.  
 The
MOSFET
Internal
Capacitances
and
High
Frequency
Models

9.  
 Frequency
Response
of
the
CS
Amplifiers

10.  
 The
CMOS
digital
Logic
Inverter

11.  







The
depleEon‐type
MOSFET

12.  
 SPICE
MOSFET
model


DE
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 2

BJT
and
MOSFET


MOSFET
features:


•  Smaller
dimensions

•  Simpler
manufacturing
process

•  Smaller
power

•  It
can
be
used
in
both
MOSFET
analog
and
digital
circuits

•  Almost
every
circuit
funcEon
can
be
realised

•  On
one
chip:
200
million
MOSFET


(Intel®
Atom™
processors
:47
million
transistors,


Intel®
Itanium®
processors:
2‐billion
transistors)

•  Mixed‐signal
design


DE
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 3

 4.1
Device
structure
and
Physical
OperaEon


4.1.1
Device
structure


Figure
4.1

Physical
structure
of
the
enhancement‐type
NMOS
transistor:


(a)  perspecEve
view;


(b)  cross‐secEon.


Typically
L
=
0.1
to
3
µm,
W
=
0.2
to
100
µm,
and
the
thickness
of
the
oxide
layer
(tox)
is
in
the
range
of
2
to
50
nm.


DE
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 4

4.1.2
OperaEon
at
VGS=0V


Two
serially
connected
dióde:
At
vDS
very
small
current
(1012
Ohm)


4.1.3Channel
forcurrent
flowing


The
p
channel
changes

to
n



Figure
4.2

The
enhancement‐type
NMOS
transistor
with
a
posiEve
voltage
applied
to
the
gate.

An
n
channel
is
induced
at
the
top
of
the
substrate
beneath
the
gate.

DE
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 5

4.1.4
Applying
smal
vDS


Figure
4.3

An
NMOS
transistor
with
vGS
>
Vt
and
with
a
small
vDS
applied.
The
device
acts
as
a

resistance
whose
value
is
determined
by
vGS.
Specifically,
the
channel
conductance
is
proporEonal

to
vGS
–
Vt’
and
thus
iD
is
proporEonal
to
(vGS
–
Vt)
vDS.
Note
that
the
depleEon
region
is
not
shown

(for
simplicity).

DE
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 6

4.1.4
Applying
small
vDS


Vt:treshhold
value,


there
is
no
current
under
this
value.

vGS
higher
than
Vt:
enhances
the
current


enhancement
op.
mode,

enhancement‐type
MOSFET


Figure
4.4

The
iD–vDS
characterisEcs
of
the
MOSFET
in
Fig.
4.3
when
the
voltage
applied

between
drain
and
source,
vDS,
is
kept
small.
The
device
operates
as
a
linear
resistor
whose

value
is
controlled
by
vGS.

DE
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 7

4.1.5
OperaEon
as
vDS
is
increased


Figure
4.5

OperaEon
of
the
enhancement
NMOS
transistor
as
vDS

is
increased.
The
induced

channel
acquires
a
tapered
shape,
and
its
resistance
increases
as
vDS
is
increased.
Here,
vGS
is

kept
constant
at
a
value
>
Vt.

DE
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 8

OperaEon
as
vDS
is
increased


Figure
4.6

The
drain
current
iD
versus
the
drain‐to‐source
voltage
vDS
for
an
enhancement‐type

NMOS
transistor
operated
with
vGS

>
Vt.


DE
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 9

4.1.6
DerivaEon
of
the
iD
–
vDS
relaEon


W  1 2 
iD = k n′ ( v
 GS − V )v − v DS , triode region (1.)

2 
t DS
L

1 W 2
iD = k n′ (vGS − Vt ) , saturation region (2.)



€ 2 L

€
W:


 
Channel
width
 εox
kn′ = µn Cox , Cox = , t ox : oxide thickness

L: 
Channel
lenght
 t ox
kn: 
process
transconductance
parameter


2010
Intel:
 link

€
2003:

Lmin


:
 
0.13μm,
(130nm
process
technology)

Wmin:
 
0.16μm,

tox


: 
 
2nm
(4
elemi
cella,
SiO2)


DE
TTK

Újabb:
32nm
,
22nm
 10

4.1.7
The

P
Channel
MOSFET


On
n
substrate
there
is
p
channel:
PMOS 
 



It
work
like
the
NMOS,
but

vGS
and
vDS
are
negaEves.

History:
PMOS
was
the
dominant
tech.
at
MOS,
but
the
NMOS
smaller
faster,,
kisebb

smaller
power
supply:
The
trend
has
chanced.

We
shuld
know
becouse
two
reason:


• 
discrete
devices


• 
complementary
MOS
(CMOS):

dominant
MOS
technologie
today


4.1.8
CMOS


Figure
4.9

Cross‐secEon
of
a
CMOS
integrated
circuit.
Note
that
the
PMOS
transistor
is
formed
in
a
separate
n‐type

region,
known
as
an
n
well.
Another
arrangement
is
also
possible
in
which
an
n‐type
body
is
used
and
the
n
device
is

formed
in
a
p
well.
Not
shown
are
the
connecEons
made
to
the
p‐type
body
and
to
the
n
well;
the
laoer
funcEons
as
the

body
terminal
for
the
p‐channel
device.



DE
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 11

4.2
Current
Voltage
CharacterisEcs


4.2.1
Circuit
Symbols


Figure
4.10



(a)  Circuit
symbol
for
the
n‐channel
enhancement‐type
MOSFET.


(b)  Modified
circuit
symbol
with
an
arrowhead
on
the
source
terminal
to
disEnguish
it
from

the
drain
and
to
indicate
device
polarity
(i.e.,
n
channel).

(c)  Simplified
circuit
symbol
to
be
used
when
the
source
is
connected
to
the
body
or
when
the

effect
of
the
body
on
device
operaEon
is
unimportant.


DE
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 12

4.2.2
The
iD
–
vDS
characterisEcs


Figure
4.11



(a)  An
n‐channel
enhancement‐type
MOSFET
with
vGS
and
vDS
applied
and
with
the
normal

direcEons
of
current
flow
indicated.


(b)  (b)
The
iD–vDS
characterisEcs
for
a
device
with
k’n
(W/L)
=
1.0
mA/V2.


Three
region:

Cutoff:
 
 
vGS
<
Vt


Triode:
 
 
vGS
≥
Vt,
vagy
vDS<
vGS
–
Vt,

triode
mode.


 
 


SaturaEon:
 
amplifier
mode


DE
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 13

 The
iD
–
vDS
characterisEcs


The
current
at
triode
mode:

W 1 2 
iD = k n′ ( v − V )v − v DS , triode region
L  2 
GS t DS

at
small
vDS
values: 
 
 
The
channel
resistance:

(linear
u‐i
relaEon)

€ v  ′W −1
W
iD = k n′ (vGS − Vt )v DS , rDS ≡ DS = k n (vGS − Vt ) ,
L iD v DS small
 L 

What
is
the
limit
of
the
saturacEon
mode?

€ € SaturaEon
mode
ib
words:

vGS
≥
Vt 
 
:induced
channel
 vGS
greater
than
Vt
and

vGD
≥
vGS
–
Vt 
:conEnuous
channel
 
vDS
does
not
fall
below
vGS

by
Vt
.


At
boundary: 
vGD
=
vGS
–
Vt


1 W 2
iD = k n′ (vGS − Vt ) , (3.)

2 L

DE
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 14


€
The
iD
–
vDS
characterisEcs


Based
on
equaEon
3.
:

 1 W 2
iD = k n′ (vGS − Vt ) ,
2 L
The
drain
current
do
not
depend
on
vDS
,
but
a
square
funcEon
of
vGS
.


€ Large
signal
model
of
the
MOSFET
:


Figure
4.12


 Figure
4.13




The
iD–vGS
characterisEc
for
an
enhancement‐type
NMOS

 Large‐signal
equivalent‐circuit
model
of
an
n‐
channel
MOSFET
operaEng
in
the
saturaEon

transistor
in
saturaEon
(Vt

=
1
V,
k’n
W/L
=
1.0
mA/V2).
 region.


DE
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 15

 4.2.3
Finite
output
resistance
in
saturaEon


In
a
real
devive
iD
depends
on
uDS
:
channel
modulaEon
(without
any
detail)


Figure
4.16


 Figure
4.17



Effect
of
vDS
on
iD
in
the
saturaEon
region.
The
MOSFET
 Large‐signal
equivalent
circuit
model
of
the
n‐channel

parameter
VA
depends
on
the
process
technology
and,
for
a
given
 MOSFET
in
saturaEon,
incorporaEng
the
output

process,
is
proporEonal
to
the
channel
length
L.
 resistance
ro.
The
output
resistance
models
the
linear

dependence
of
iD
on
vDS
.


DE
TTK
 16

4.2.4
CharacterisEc
of
the
p
channel
MOSFET
(enhancement
type)



Figure
4.18



(a)  Circuit
symbol
for
the
p‐channel
enhancement‐type
MOSFET.


(b)  Modified
symbol
with
an
arrowhead
on
the
source
lead.

(c)  Simplified
circuit
symbol
for
the
case
where
the
source
is
connected
to
the
body.


(d)  The
MOSFET
with
voltages
applied
and
the
direcEons
of
current
flow
indicated.


Note
that
vGS
and
vDS
are
negaEve
and
iD
flows
out
of
the
drain
terminal.

DE
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 17

4.2.6
Temperature
effects


Both
:
Vt
and
k`
are
temperature
dependents


Vt
:
decreases
if
the
T
increases
(2mV/°C)
(
T
raises

iD
raises
).

k`
:
decreases
if
the
T
increases
so:
iD
also
decreases.
(dominant
effect)


4.2.7
Breakdown
and
Input
ProtecEon


1.
The
pn
juncEon
between
the
drain
and
substrate

(
at
raising
vD)
suffers
avalanche
breakdown


(20..150V)
(weak
avalanche) 
(iD
raises
rapidly)


2.
vD
növeléskor
a
the
depleEon
region
extends

trough
the
channel
to
the
source
:breakdown

(20V)

(punch‐trough)
 
 
(iD
raises) 
 
(non
permanent
damage)


3.
If

vGS
reaches
30V

gate
oxide
breakdown
(permanent
damage).

(small
capacitance
at
gate:
small
amount
of
charge
to
reach
the
30V
:
serious
problem)


Gate
protecEon
devices
are
included

for
MOS
IC‐s.


DE
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 18

4.3
MOSFETs
at
DC



Examples


4.2
‐‐‐
4.7


DE
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 19

4.4
MOSFET
as
an
Amplifier
and
as
a
Switch


Figure

4.26



(a)  Basic
structure
of
the
common‐source
amplifier.


(b)  Graphical
construcEon
to
determine
the
transfer
characterisEc
of
the
amplifier
in
(a).


DE
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 20

4.4.1
Large
signal
operaEon,
A
transfer
characterisEcs


Figure

4.26

(Con4nued)


(c)
Transfer
characterisEc
showing
operaEon
as
an
amplifier
biased
at
point
Q.

DE
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 21

Load
line:


At
the
output:


v DS = VDD − RD iD ,
VDD 1
iD = − v DS ,
RD RD
€

DE
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 22

4.4.3
OperaEon
as
a
switch


Switched
off
state:
 
vI
<
Vt



 
 
 
XA
region



 
Then: 
vO
=
VDD




Switched
on
state: 
vI
≅
VDD



 
 
 
At
C
,



 
then:
vO
: 
very
small


The
Common
Source
MOS
can
be
used
as
an
inverter
:
vO
:
0V...VDD.

(In
4.10
detailed
analisis)


DE
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 23

 4.4.4
OperaEon
as
a
Linear
Amplifier


We
should
shiy
the
quesEon
point
to
:

Q
–
linear
region.


The
definiEon
of
the
gain:

dv o
Av = ,
dv I v I = vGS

Choosing
Q
:
symmetrical
output
swing
.


4.4.5
AnaliEcal
Expression
for
the
Transfer
characterisEc


X‐A
region:
Cutoff
mode.
If
vGS
<
Vt

then
uO=VDD.


A‐Q‐B
: 
SaturaEon
mode.


 1 W 2
iD = k n′ (v I − Vt ) ,
2 L

From
the
circuit:
 v DS = VDD − RD iD ,
€ DE
TTK
 24

AnaliEcal
Expression
for
the
Transfer
characterisEc



SubsEtuEng

iD
:


1 W 2
vO = VDD − RD kn′ (v I −Vt ) ,
2 L

B‐C
: 
Triode
mode.

W  1 2 
€ iD = k n′ ( v GS − Vt )v DS − v DS ,
L 2 
Then
uO:

W 1 2
€ vO = VDD − RD kn′ ( GS t ) DS v DS ,
v −V v −
L 2 
Ayer
some
simplificaEon:




€ rDS r
vO = VDD ≡ VDD DS , if rDS ‹‹RD
rDS + RD RD

DE
TTK
 25

€
 4.5
Biasing
in
MOS
Amplifiers

Task
Sezng
the
operaEng
point
parameters:
ID
and
UD
.


4.5.1
Biasing
by
fixing
VGS



Wrong
method.
Why?


1 W 2
iD = µn Cox (v I − Vt ) ,
2 L

Cox , W , L, Vt
€
Large
spreads
in
parameters

of
the
same
type
of
device.

€ especially
at
discrete
devices.

(fig.
4.29.)


Figure
4.29



The
use
of
fixed
bias
(constant
VGS)
can
result
in
a
large

variability
in
the
value
of
ID.


Devices
1
and
2
represent
extremes
among
units
of
the

same
type.

DE
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 26

 4.5.2
Biasing
by
fixing
VG
and
with
an
RS


VG
=
VGS
+
RSID,


Figure
4.30



Biasing
using
a
fixed
voltage
at
the
gate,
VG,


and
a
resistance
in
the
source
lead,
RS:


(a)  basic
arrangement;


(b)  reduced
variability
in
ID;


(c)  pracEcal
implementaEon
using
a
single
supply;


(d)  coupling
of
a
signal
source
to
the
gate
using
a
capacitor
CC1;


(e)  pracEcal
implementaEon
using
two
supplies.

DE
TTK
 27

4.5.2
Biasing
using
a
constant
current
source

Figure
4.33



(a)  Biasing
the
MOSFET
using


a
constant‐current
source
I.


(b)
ImplementaEon
of
the
constant‐current


source
I
using
a
current
mirror.


RG:
nx1MOhm


Current
mirror:


1 W  2 1 W  2
ID1 = k n′   (v I − Vt ) , I = ID 2 = k n′   (v I − Vt ) ,
2  L 1 2  L 2

V + VSS − VGS (W /L) 2

ID1 = IREF = DD , I = IREF = ,
R (W /L)1
€ €
DE
TTK
 28


€ €
 4.6
Small‐signal
operaEon
and
models

What
is
the
slope
at
Q:

1 W 2
vGS = VGS + v gs, iD = k n′ (v I − Vt ) ,
2 L

1 W 2
€ iD = k n′ (VGS + v€gs − Vt ) =
2 L
1 W 2 W 1 W
= kn′ (VGS − Vt ) + kn′ (VGS − Vt )v gs + kn′ v gs2,
2 L L 2 L
€ First
term:
DC
ID.


For
the
second
and
third
term:

€ 1 ′W 2 ′W v gs‹‹ 2(VGS − Vt )
kn v gs ‹‹ kn (VGS − Vt )v gs
2 L L
Figure
4.35



v gs‹‹ 2VOV , VOV : overdrive voltage
Small‐signal
operaEon
of
the
enhancement
MOSFET
amplifier.

€
€
If
this
small
signal
condiEon
saEsfies:

 We
can
express:

linear
behaviour:
 €id W
= gm = kn′ (VGS − Vt ), : transzkonduktace
iD = ID + id , v gs L
W
W gm = kn′ VOV ,
id = k n′ (VGS − Vt )v gs, DE
TTK
 L 29

L
€ €
4.6.3
The
voltage
gain


SeparaEng
the
AC
and
DC
components:

v DS = VDD − RD iD = VDD − RD ( ID + id ) = VDD − RD ID − RD id = VD − RD id ,

The
AC
signal
component:
 v d = −RD id = −gm v gsRD ,

€ The
voltage
gain:


€ vd
Av ≡ = −gm RD ,
v gs

Figure
4.36



Total
instantaneous
voltages
vGS
and
vD
for
the
circuit
above


DE
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 30

4.6.4
SeparaEng
the
DC
and
AC
analyzis


4.6.5
Small
signal
models


Figure
4.37



Small‐signal
models
for
the
MOSFET:


(a)  neglecEng
the
dependence
of
iD
on
vDS
in
saturaEon
(the
channel‐length
modulaEon
effect);
and


(b)  including
the
effect
of
channel‐length
modulaEon,
modeled
by
output
resistance
ro
=
|VA|
/ID.


DE
TTK
 31

4.6.6
The
transconductance

Remark:


W 
For
big
gm:


Expression
for
gm:
 gm = kn′ VOV ,
L • large
W

• small
L

Another
expression:
 Remark:

€ gm = kn′ W /L ID , • For
a
given
MOSFET:
proporEonal



to
the
square
root
of
ID
.

• At
a
given
ID:
proporEonal
to
square
root



of
W/L
.

€
CalculaEon
for
gm
:


ID=0.5mA,
k=120uA/V2,
 
W/L=1,
 
gm=0.35mA/V



 
 
 
 
W/L=100,

gm=3.5mA/V

In
contrast
at
a
BJT
IC=0.5mA
:
20mA/V
(much
higher)


Another
useful
gm
expression:
 2ID 2I
gm = = D,
VGS − Vt VOV

Design:
W/L,
ID,
VOV
:
We
can
choose
two
parameters
independently
.


€
DE
TTK
 32

4.6.7
The
T
model


Figure
4.39



Development
of
the
T
equivalent‐circuit
model
for
the
MOSFET.
For
simplicity,
ro

has
been
omioed
but
can
be
added
between
D
and
S
in
the
T
model
of
(d).

DE
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 33

4.6.8
The
body
effect


If
the

Substrate
does
not
connected
to
the
Source:
Body
effect


gmb = χ gm , χ : 0.1...0.3,
Figure
4.41



Small‐signal
equivalent‐circuit
model
of
a
MOSFET
in
which
the
source
is
not
connected
to
the

body.

€
DE
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 34

4.7
Single
stage
MOS
amplifiers


AssumpEon:
There
is
no
body
effect.
(The
Substarte
is
connected
to
the
Source)


4.7.1The
basic
structure


Figure
4.42



Basic
structure
of
the
circuit
used
to
realize
single‐stage
discrete‐circuit
MOS
amplifier

configuraEons.


DE
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 35

4.7.2
Qualifying
of
Amplifiers


deatailed
definiEons
:Book!


Circuit
models:


DE
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 36

4.7.3
The
common
source
(CS)
amplifier


The
circuit:


The
circuit
model:


Rin = RG ,

Av = −gm ( ro RD RL ),
€
Rout = ro RD , ro ››RD
€

DE
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 37

4.7.4
the
common
source
(CS)
amplifier
with
source
resistor


Rin = RG ,
Figure
4.44



(a)  Common‐source
amplifier
with
a
resistance
RS
in
the
source
lead.


(b)  Small‐signal
equivalent
circuit
with
ro
neglected.
 gm ( ro RD RL )
Av = − ,
1+ gm RS
€

DE
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 38

€
4.7.5
The
common
gate
(CG)
amplifier


The
circuit: 
 
 
 
 
 
 
 
The
model:


1
Rin = ,
gm

Av = gm ( RD RL ),

€ Rout = Ro = RD ,
DE
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 39

€

€
 4.7.6
The
common
drain
(CD)
amplifier


Rin = RG ,

RL ro
Av = − ,
Figure
4.46


 € 1
(RL ro ) + g
(a)  A
common‐drain
or
source‐follower
amplifier.

 m

(b)  Small‐signal
equivalent‐circuit
model.

 RL=∞,
ill.
ro=∞
Av=?


(c)  Small‐signal
analysis
performed
directly
on
the
circuit.


€ 1 1
(d)  Circuit
for
determining
the
output

resistance
Rout
of
the
source
follower.
 Rout = ro ≅ ,
gm gm
DE
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 40

4.7.7
Summary


1.  CS
configuraEon:
Best
suited
for
obtaining
the
bulk
of
the
gain
required.

Can
be
used
2
or
3
stages.

2.  CS
config
including
RS
:
Beoer
parameters,
but
at
the
expense
of
gain
reducEons.


3.  CG
config:
Small
input
resitance.
High
frequency
bandwith.



4.  CD
config:
Source
follower,connecEng
high
resistance
source
to
low
load.


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 4.8
The
MOSFET
Internal
capacitances
and
high
frequency
model



Physical
origin
of
capacitances:



1.
Gate
–
channel
capacitance:
Cox



2.
Source
‐
Body,
Drain
–
Body







depleEon
layer
capacitances


4.8.1
A
Gate
capacitances
 4.8.2JuncEon
Capacitances

Cgs:
gate
–
source

 Csb:
source
–
body

Cgd:
gate
–
drain
 Cdb:
drain


–
body


s

Details:
Book!
 Details
Book!


Figure
4.47



(a)  High‐frequency
equivalent
circuit
model
for
the
MOSFET.


(b)  The
equivalent
circuit
for
the
case
in
which
the
source
is


connected
to
the
substrate
(body).


(c)
The
equivalent
circuit
model
of
(b)
with
Cdb
neglected


DE
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(to
simplify
analysis).
 42

4.8.4
A
MOSFET
Unity‐Gain
frequency
(fT)

Without
details:
 fT
typical
values:


gm
fT = , 
100MHz
–
5





μm
process

(old)

2π (Cgs + Cgd )


nx1GHz
–
0.13
μm
process
(today)


4.8.5
Összefoglalás


Model:

€

DE
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 4.9
Frequency
response
of
the
CS
amplifier


4.9.1
The
three
fr.
bands


Bandwith:
(BW)
at
‐3dB
values

BW
=
fH
–
fL

In
pracEce:
BW
≅
fH
,
(fH
››
fL)


Gain
Bandwidth
product:


GB ≡ Amidband BW ,

Figure
4.49

(a)
CapaciEvely
coupled
common‐source
amplifier.
(b)
A
sketch
of
the
frequency
response

of
the
amplifier
in

(a)
delineaEng
the
three
frequency
bands
of
interest.


DE
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€ 44

4.9.2
The
high
frequency
response


Figure
4.50

Determining
the
high‐frequency
response
of
the
CS
amplifier:


(a)  equivalent
circuit;


(b)  the
circuit
of
(a)
simplified
at
the
input
and
the
output;



DE
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 45

The
high
frequency
response


Figure
4.50

(Con4nued)


(c)
the
equivalent
circuit
with
Cgd
replaced
at
the
input
side
with
the
equivalent
capacitance
Ceq;

(d)
the
frequency
response
plot,
which
is
that
of
a
low‐pass
single‐Eme‐constant
circuit.


DE
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4.9.3
The
low
frequency
response


Figure
4.51

Analysis
of
the
CS
amplifier
to
determine
its
low‐frequency
transfer
funcEon.


For
simplicity,
ro
is
neglected.

DE
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 The
low
frequency
response


Figure
4.52

Sketch
of
the
low‐frequency
magnitude
response
of
a
CS
amplifier
for

which
the
three
break
frequencies
are
sufficiently
separated
for
their
effects
to

appear
disEnct.


DE
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 48

4.11
The
depleEon‐type
MOSFET


Figure
4.60

The
current‐voltage
characterisEcs
of
a
depleEon‐type
n‐channel
MOSFET
for
which
Vt
=
–4
V

and
k′n(W/L)
=
2
mA/V2:
(a)
transistor
with
current
and
voltage
polariEes
indicated;
(b)
the
iD–vDS

DE
TTK

characterisEcs;
(c)
the
iD–vGS
characterisEc
in
saturaEon.
 49

Different
types
of
MOSFETs


Figure
4.62



Sketches
of
the
iD–vGS
characterisEcs
for
MOSFETs
of
enhancement
and
depleEon
types,
of
both

polariEes
(operaEng
in
saturaEon).
Note
that
the
characterisEc
curves
intersect
the
vGS
axis
at

Vt.
Also
note
that
for
generality
somewhat
different
values
of
|Vt|
are
shown
for
n‐channel
and

p‐channel
devices.

DE
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4.12
The
SPICE
MOSFET
model

Simple
model
:
square‐law
model
(long
channel)


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