Chapter 6

The Field Effect Transistor

 MOSFETs vs BJTs
BJTs MOSFETs
• Three different • Mostly widely used
currents in the device: today
IC, IB and IE • Low power
• Consume a lot of • Very small device (nm)
power • Simple manufacturing
• Large size device process
• Only 1 current, ID
MOS Field Effect Transistor
 In the MOSFET, the current is controlled by an electric
field applied perpendicular to both the semiconductor
surface and to the direction of current.
 The phenomenon is called the field effect.
 The basic transistor principle is that the voltage between
two terminals, provides the electric field, and controls
the current through the third terminal.

metal
oxide

substrate
 Two-Terminal MOS Structure
 A MOS capacitor with a p-type semiconductor substrate: the top
metal terminal, called the gate, is at a negative voltage with
respect to the substrate.
 A negative charge will exist on the top metal plate and an electric
field will be induced.
 If the electric field penetrates the semiconductor, the holes in the
p-type semiconductor will experience a force toward the oxide-
semiconductor interface and an accumulation layer of holes will
exist
 Two-Terminal MOS Structure
 The same MOS capacitor, but with the polarity of the applied
voltage reversed.
 A positive charge now exists on the top metal plate and the
induced electric field is in the opposite direction
 If the electric field penetrates the semiconductor, holes in the p-
type material will experience a force away from the oxide-
semiconductor interface.
 Two-Terminal MOS Structure
 As the holes are pushed away from the interface, a negative
space-charge region is created.
 This region of minority carrier electrons is called an electron
inversion layer.
 The magnitude of the charge in the inversion layer is a function
of the applied gate voltage, hence the larger voltage is applied,
the wider it becomes
 NMOS Enhancement Mode
● Transistor Structure
 The gate, oxide, and p-type substrate are the same as those of a MOS
capacitor.
 There are two n-regions, called the source and drain terminal.
 The current in a MOSFET is the result of the flow of charge in the
inversion layer, called the channel region, adjacent to the oxide-
semiconductor interface.
 NMOS Enhancement Mode
 If a large enough positive voltage gate voltage is applied, an electron
inversion layer connects the n-source to the n-drain.
 A current can then be generated between the source and drain
terminals.
 Since a voltage must be applied to the gate to create the inversion
charge, this transistor is called an enhancement mode MOSFET.
 Since the carriers in the inversion layer are electrons, this device is
called an n-channel MOSFET (NMOS).
 Ideal MOSFET Current-Voltage Characteristics
– NMOS Device
 The threshold voltage of the n-channel MOSFET, denoted as VTH or VTN,
is defined as the applied gate voltage needed to create an inversion
charge.
 If the VGS < VTN, the current in the device is essentially zero.
 If the VGS > VTN, a drain-to-source current, ID is generated as an induced
electron inversion layer / channel is created
Ideal MOSFET Current-Voltage Characteristics –
NMOS Device
Direction of
Electric field

holes experience force same

direction of electric field, leaving
an electron inversion layer

 A positive but small drain voltage, VDS creates a reverse-biased

drain-to-substrate pn junction, depletion region width increases
 At the drain end, the inversion layer bridges the depletion region,
providing a path for the current to flow.
 So current flows through the channel region, not through a pn
junction.
 Reverse-Biased pn Junction
• There is an increase of the electric field in the depletion region, the
number of charges increases too since the width of the depletion
increases.
W
-- ++
p - - E ++ n Equilibrium

-- ++

- - - - ++ ++
ET
p - - - - ++ ++ n Reverse Biased
- - - - ++ ++

WR
Ideal MOSFET Current-Voltage Characteristics –
NMOS Device

● The iD versus vDS characteristics for small values of vDS

 When vGS < VTN, the drain

current is zero.
 When vGS > VTN, the channel
inversion charge is formed
and the drain current
increases with vDS
 With a larger gate voltage, a
larger inversion charge
density is created, and the
drain current is greater for a
given value of vDS
 Ideal MOSFET Current-Voltage Characteristics –
NMOS Device

● In the basic MOS structure for vGS

> VTN with a small vDS:
 The thickness of the inversion
channel layer qualitatively
indicates the relative charge
density.
 Which for this case is essentially
constant along the entire
channel length.
 VDS +
-

S - VGS + G + VGD - D

-------------------------

VGS = VG – VS
VGD = VG – VD
But VGD = VGS – VDS
VGD = VG – VS – VD +VS
So, if VDS is small, VGD VGS, we have
approximately equal distribution of channel
inversion layer
 Ideal MOSFET Current-Voltage Characteristics –
NMOS Device
VGD = VGS – VDS
 When the drain voltage vDS increases,
the voltage drop across the oxide near
the drain terminal decreases – no
longer uniform distribution.
 It means that the induced inversion
charge density near the drain also
decreases.
 It causes the slope of the iD versus vDS
curve to decrease.
As VDS increases, the channel at the drain end reaches the pinch-off point and the
value of VDS that causes the channel to reach this point is called saturation
voltage VDSsat

VGD = VGS – VDS sat

At the pinch off point, VGD = VTN

VGD = VGS – VDS sat
VTN = VGS – VDS sat
Hence,

VDSsat = VGS - VTN

 Ideal MOSFET Current-Voltage Characteristics –
NMOS Device

 When vDS becomes larger than vDS(sat), the

point in the channel at which the inversion
charge is zero moves toward the source
terminal.
 In the ideal MOSFET, the drain current is
constant for vDS > vDS(sat).
 This region of the iD versus vDS characteristic is
referred to as the saturation region.
 The electrons travel through the channel
towards the drain but then they are swept by
the electric field to the drain contact
 Ideal MOSFET Current-Voltage Characteristics –
NMOS Device

 The region for which

vDS < vDS(sat) is known
as the non-saturation
or triode region.
 The ideal current-
voltage characteristics
in this region are
described by the
equation:

I D  K n [2VGS  VTN VDS  VDS ]

2

Kn = conduction parameter k 'n W

Kn  .
2 L
 Ideal MOSFET Current-Voltage Characteristics –
NMOS Device

 In the saturation
region, the ideal
current-voltage
characteristics for
vGS > VTN are
described by the
equation:

I D  K n VGS  VTN 
2
 LIST OF FORMULAS: NMOS
TRIODE OR NON-SATURATION REGION

I D  K n [2VGS  VTN VDS  V DS ]

2

SATURATION REGION

I D  K n VGS  VTN 
2
and VDSsat = VGS - VTN

Where

k 'n W
Kn  .
2 L
Circuit Symbols and Conventions –
NMOS

FET is a voltage controlled device

meaning the voltage VGS determines
the current flowing, ID
Circuit Symbols and Conventions –
PMOS Enhancement mode
 LIST OF FORMULAS: PMOS

TRIODE OR NON-SATURATION REGION

I D  K p [ 2VSG  VTP VSD  VSD ]

2

SATURATION REGION VSG > |VTP |


I D  K p VSG  VTP 2
and VSDat = VSG +VTP

Where

k' p W
Kp  .
2 L
• NMOS • PMOS
o VTN is POSITIVE o VTP is NEGATIVE
o VGS > VTN to turn on o VSG > |VTP| to turn on
o Triode/non-saturation o Triode/non-saturation
region region
I D  K p [2VSG  VTP VSD  VSD ]
2
I D  K n [2VGS  VTN VDS  V DS ]
2

o Saturation region  K p VSG region

VTP 
2
I D  K n VGS  VTN  o
I DSaturation
2

o VDSsat = VGS - VTN o VSDsat = VSG + VTP

DC analysis of FET
MOSFET DC Circuit Analysis - NMOS

 The source terminal is at

ground and common to
both input and output
portions of the circuit.
 The CC acts as an open
circuit to dc but it allows
the signal voltage to the
gate of the MOSFET.

 In the DC equivalent circuit, the gate current into the transistor is

zero, the voltage at the gate is given by a voltage divider principle:
VG = VTH = R2 VDD
R1 + R2
MOSFET DC Circuit Analysis - NMOS
1. Calculate the value of VGS

2. Assume the transistor is biased in the saturation

region, the drain current:

I D  K n VGS  VTN 
2

3. Use KVL at DS loop

IDRD + VDS – VDD = 0
VDS = VDD - IDRD

4. Calculate VDSsat = VGS - VTN

5. Confirm your assumption:

If VDS > VDS(sat) = VGS – VTN, then the transistor is biased in the saturation region.
If VDS < VDS(sat), then the transistor is biased in the non-saturation region.
 EXAMPLE:
Calculate the drain current and drain to source voltage of a common source circuit
with an n-channel enhancement mode MOSFET. Assume that R 1 = 30 k, R2 = 20 k,
RD = 20 k, VDD = 5V, VTN = 1V and Kn = 0.1 mA/V2
1. Calculate the value of VGS

2. Assume the transistor is biased in the saturation

region, the drain current:
I D  K n VGS  VTN 
2

I D  0.1(2  1) 2  0.1mA
3. Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3 V

4. Calculate VDSsat = VGS – VTN = 2 – 1 = 1V

5. Confirm your assumption: VDS > VDSsat, our assumption that the transistor is
in saturation region is correct
 EXAMPLE
• The transistor has parameters
VDD = 10V
VTN = 2V and Kn = 0.25mA/V2.
• Find ID and VDS
R1 = 280k RD = 10k

R2 = 160k
 Solution
1. Calculate the value of VGS

KVL at GS loop: VGS – VTH + 0 = 0  VGS = VTH

2. Assume the transistor is biased in the saturation region, the drain current:
I D  K n VGS  VTN 
2

I D  0.25(3.636  2) 2  0.669mA
3. Use KVL at DS loop
IDRD + VDS – VDD = 0
VDS = VDD – IDRD = 3.31 V
4. Calculate VDSsat = VGS – VTN = 3.636 – 2 = 1.636 V
5. Confirm your assumption: VDS > VDSsat, our assumption that the transistor is
in saturation region is correct
Answer: ID = 0.669 mA and VDS = 3.31 V
The MOSFET in the circuit shown has parameters, and . Assume that, k, R2 k and
RD = 6 k . Calculate IDQ and VDSQ .
 Solution
1. Calculate the value of VGS
KVL at GS loop: VGS – VTH + 0 = 0  VGS = 6.12 V

2. Assume the transistor is biased in the saturation region, the drain current:
I D  K n VGS  VTN 
2

I D  0.03(6.12  0.8) 2  0.85mA

3. Use KVL at DS loop
IDRD + VDS – 8 = 0
VDS = 8 – 6(0.85) = 2.9 V

4. Calculate VDSsat = VGS – VTN = 6.12 – 0.8 = 5.32 V

5. Confirm your assumption: VDS < VDSsat, our assumption that the transistor is
in saturation region is NOT CORRECT
That means our transistor is in non-saturation mode: Go back to step 2

I D  K n [2VGS  VTN VDS  V DS ]

2

ID = 0.03 2 ( 5.32 ) (8 – 6ID) – (8 – 6ID)2

33.33 ID = 10.64 (8 – 6ID) – (64 – 96ID + 36ID2

33.33 ID = 85.12 – 63.84 ID – 64 + 96ID - 36ID2 ID = 0.75 mA

36
3. IGo
D +
2
1.17toIDDS
back – 21.12
loop = 0 ID = - 0.78 mA
IDRD + VDS – 8 = 0
VDS = 8 – 6(0.75) = 3.5 V

Answer: ID = 0.75 mA and VDS = 3.5V