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2.1 Introduction
Symbols
NMOS
PMOS
1
Threshold voltage (Vt):
The voltage at which an MOS device begins to conduct ("turn
on")
(1) Devices that are normally cut-off with zero gate bias are
classified as "enhancement-mode "devices.
(2) Devices that conduct with zero gate bias are called
"depletion-mode "devices.
2
2.1.1 NMOS Enhancement Transistor
Consist of
(1) Moderately doped p-type silicon substrate
(2) Two heavily doped n + regions, the source and drain, are
diffused.
(3) Channel is covered by a thin insulating layer of silicon dioxide
(SiO2) called " Gate Oxide "
(4) Over the oxide is a polycrystalline silicon (polysilicon) electrode,
referred to as the "Gate"
Features
(1) Since the oxide layer is an insulator, the DC current from the
gate to channel is essentially zero.
(3) Since SiO2 has low loss and high dielectric strength, the
application of high gate fields is feasible.
In operation
(1) Set Vds > 0 in operation
(2) Vgs =0 no current flow between source and drain. They are
insulated by two reversed-biased PN junctions (see Fig 2.3).
3
(3) When Vg > 0 , the produced E field attracts electrons toward
the gate and repels holes.
4
Electrically
(1) An MOS device can be considered as a voltage-controlled
switch that conducts when Vgs >Vt (given Vds>0)
At the drain end , only the difference between the gate and
drain voltage is effective
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Pinch-off
(1) Vds > Vgs-Vt => Vgd < Vt => Vd > Vg –Vt (Vg is not big
enough)
Conducting mode
(1) ”cut-off ” region : Ids ≈ 0 , Vgs < Vt
(2) ” Nonsaturated” region : weak inversion region, when Ids
depends on Vg & Vd
(3) ”Saturated“ region: channel is strongly inverted and Ids is
ideally independent of Vds (pinch-off region)
(4) ”Avalanche breakdown” (pinch-through) : very high Vd => gate
has no control over Ids
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2.1.2 PMOS Enhancement Transistor
(1) Vg < 0
(3) Vd < 0 , which sweeps holes from the source through the
channel to the drain .
A function of
(1) Gate conductor material
(2) Gate insulator material
(3) Gate insulator thickness
(4) Impurity at the silicon-insulator interface
(5) Voltage between the source and the substrate Vsb
(6) Temperature
a. -4 mV/’C – high substrate doping
b. -2 mV/’C – low substrate doping
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2.2 MOS equations
, 0< Vgs-Vt<Vds
2
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β: MOS transistor gain factor
Function of (1) process parameter (2) device geometry
Example
Typical CMOS
◎(~1μ) process
°
(3) tox=200 Α
µε W W
βn = = 88.5 µΑ / V
2
tox
L L
2 W µΑ
◎ µ p = 180 cm V − sec => β p = 31.9
L V2
βN
◎ = 2.8 (2~3 depending on process)
βp
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2.2.2. Seven Second-order Effect
LEVEL: 1,2,3
(1) Basic DC Equations + Some second-order effects
(2) Based on device physics
(3) Add more parameters to match real circuits
A. Channel-length modulation
ε si
Lshort = 2 (Vds − (Vgs − Vt ))
qN A
=>L↓=>β↑=> Ids↑
(Vgs − Vt ) (1 + λVds )
K W
I ds =
2
2 L
µε
With K = : process gain factor
tox
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C. Threshold voltage (Vt) – Body effect (Vsb)
2ε si qN A (2φ b + VSB )
Vt = V fb + 2φ b +
Cox
[
=> Vt = Vt 0 + γ 2φb + VSB − 2φ b ]
(1) Vsb : Substrate bias
(2) Vt0 : Vt at Vsb=0
(3) γ: a constant which describes the substrate bias effect
tox 1
(range:0.4~1.2) γ = 2qε si N A = 2 qε si N A
ε ox Cox
(4) SPICE
γ: GAMMA in SPICE model
Vto : VT0
NA : NSUB
ψs = 2ψb : PHI (the surface potential at the onset of strong
inversion)
Subthreshold region
Others:
- Mobility variation
- Fowler-Nordheim Tunneling
- Impact Ionization (Hot electrons effect)
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2.2.3 MOS Models
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2.3 CMOS inverter DC characteristics
← turn on →
V gs = V g − V DD < − V tp
13
Both transistors are “on”
P = fcv ⋅ α
2
(Switching activity)
Vinn = Vinp
⇒ Vout = V DD
p: V gs = Vin − V DD
Vds = Vout − V DD
14
(Vout − V DD ) 2
∴ I dsp = − β p [(Vin − V DD − Vtp )(Vout − V DD ) − ]
2
V gs − Vtp Vds
µ pε W p
with βp = ( )
t ox Lp
V DD β
⇒ Vout = (Vin − Vtp ) + (Vin − Vtp ) 2 − 2(Vin − − Vtp )V DD − n (Vin − Vtn ) 2
2 βp
βn
V DD + Vtp + Vtn
βp
⇒ Vin =
βn
1+
βp
possible Vout
15
(V DD − Vin ) − Vtp > (V DD − Vout )
P-MOS
V gs − Vtp > Vds
Negative value
V DD
⇒ Vin is fixed at , Vout varies
2
⇒ make the o/p transition very steep
1
I dsp = − β p (Vin − V DD − Vtp ) 2
2
Vout 2
I dsn = β n [(Vin − Vtn )Vout − ]
2
βp
⇒ Vout = (Vin − Vtn ) − (Vin − Vtn ) 2 − (Vin − V DD − Vtp ) 2
βn
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2.3.1 βn βp ratio ( watch Eq.(2.24) )
Wn
βn Ln
β p ↔ Wp
Lp
⇒ I ds ∝ T −1.5
17
V IL = 2.3
V IH = 3.3
18
2.4 Static Load MOS inverters
Resistor-load inverter
Current-source-load inverter
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2.6 The Transmission Gate
(PMOS)
(NMOS)
Vout = V SS
V gs = 0 V
I ds = 0
Vout remains at V SS
S=1 (Vdd )
V gs = V DD (initially)
V gs = 5 V > Vt ⇒ charge
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S=0 (open circuit) , Vout remains at V DD − Vtn (Vdd ) ,
S=1
Vin = 0
Vout = V DD − Vtn (Vdd )
S=0 (close)
Vin = V DD , current
Vout to V DD
charge (C_load)
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S=0 (close)
Vin = V ss ,
Vout = V DD
Discharge C_load
until through p-device
until Vout = Vtp (V ss ) , at which point the transistor stops
conducting
Vin = V DD , Vout = Z
(2) S=1 ( S = 0) :
N,P devices are ‘ON’
Vin = V SS , Vout = V SS , Vin = V DD , Vout = V DD
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(1) Capacitor loaded circuit
Cload at Vss
* Cload is large
When S is ON NMOS , S = 0 1
PMOS , S = 1 0
(PMOS)
It starts at ‘saturation’ ‘nonsaturation’
as V gsp − Vtp > Vdsp
Vout↑(transmission gate)
(NMOS)
always at ‘saturation’ , ∵ Vdsn = V gsn
Rise
After Vout → V DD − Vtn , NMOS is ‘off’
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Three regions of operation :
a. Region A
p : constant current source
n : current varies inversely with Vout
b. Region B
both currents vary linearly (inverse) with Vout
c. Region C
p-current varies inverse linearly with Vout
p-current
Combined
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