ELEC343

Digital Systems Design

Lecture 9
CMOS Fabrication
Lecturer: Dr. Yinan KONG
Office: E6A241 – Electronic Engineering
Email: yinan.kong@mq.edu.au
Phone: 9850 1094
Fax: 9850 9128

Jul-13 ELEC343 - Digital Systems Design

 Introduction
• Integrated circuits: many transistors on one
chip.
– Very Large Scale Integration (VLSI): very many

• Field Effect Transistor (FET)

• Bipolar Junction FET (BJT)

Jul-13 ELEC343 - Digital Systems Design

 Introduction
• Metal Oxide Semiconductor (MOS) transistor
– Fast, cheap, low-power transistors
– Complementary: mixture of n- and p-type leads to
less power

• This lecture is for ASIC design

How to build your own simple CMOS chip
– CMOS transistors
– Building logic gates from transistors
– Transistor layout and fabrication
Jul-13 ELEC343 - Digital Systems Design
 Silicon Lattice
• Transistors are built on a silicon substrate
• Silicon is a Group IV material
• Forms crystal lattice with bonds to four
neighbors
Si Si Si

Si Si Si

Si Si Si

Jul-13 ELEC343 - Digital Systems Design

 Dopants
• Silicon is a semiconductor
• Pure silicon has no free carriers and conducts
poorly
• Adding dopants increases the conductivity
• Group V (Arsenic): extra electron (n-type)
• Group III (Boron): missing electron, called hole
(p-type)
Si Si Si Si Si Si
- +

+ -
Si As Si Si B Si

Si Si Si Si Si Si

Jul-13 ELEC343 - Digital Systems Design

 p-n Junctions
• A junction between p-type and n-type
semiconductor forms a diode.
• Current flows only in one direction

p-type n-type

anode cathode

Jul-13 ELEC343 - Digital Systems Design

 nMOS Transistor
• Four terminals: gate, source, drain, body
• Gate – oxide – body stack looks like a
capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– n+ is called n+ diffusion
– Even though gate is Source Gate Drain
Polysilicon
no longer made of metal SiO2

n+ n+

p bulk Si

Jul-13 ELEC343 - Digital Systems Design

 nMOS Operation
• Body is commonly tied to ground (0 V)
• When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source Gate Drain
Polysilicon
SiO2

0
n+ n+
S D
p bulk Si

Jul-13 ELEC343 - Digital Systems Design

 nMOS Operation
• When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source Gate Drain
Polysilicon
SiO2

1
n+ n+
S D
p bulk Si

Jul-13 ELEC343 - Digital Systems Design

 pMOS Transistor
• Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source Gate Drain
Polysilicon
SiO2

p+ p+

n bulk Si

Jul-13 ELEC343 - Digital Systems Design

 Power Supply Voltage
• GND = 0 V
• In 1990’s, VDD = 5V
• VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
• VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …

Jul-13 ELEC343 - Digital Systems Design

 Transistors as Switches
• We can view MOS transistors as electrically
controlled switches
• Voltage at gate controls path from source to
drain g=0 g=1

d d d
nMOS g OFF
ON
s s s

d d d

pMOS g OFF
ON
s s s

Jul-13 ELEC343 - Digital Systems Design

ELEC343
Digital Systems Design

Schematics

Lecturer: Dr. Yinan KONG

Office: E6A241 – Electronic Engineering
Email: yinan.kong@mq.edu.au
Phone: 9850 1094
Fax: 9850 9128

Jul-13 ELEC343 - Digital Systems Design

 CMOS Inverter

A Y VDD
0
1

A Y

A Y
GND
Jul-13 ELEC343 - Digital Systems Design
 CMOS Inverter

A Y VDD
0
1 0 OFF
A=1 Y=0

ON
A Y
GND
Jul-13 ELEC343 - Digital Systems Design
 CMOS Inverter

A Y VDD
0 1
1 0 ON
A=0 Y=1

OFF
A Y
GND
Jul-13 ELEC343 - Digital Systems Design
 CMOS Inverter

VDD
pull-up network
or
p network
A Y
pull-down network
or
n network

GND
Jul-13 ELEC343 - Digital Systems Design
 CMOS NAND Gate
A B Y
0 0
0 1 Y
1 0 A
1 1
B

Jul-13 ELEC343 - Digital Systems Design

 CMOS NAND Gate
A B Y
0 0 1 ON ON
0 1 Y=1
A=0
1 0 OFF
1 1
B=0
OFF

Jul-13 ELEC343 - Digital Systems Design

 CMOS NAND Gate
A B Y
0 0 1 OFF ON
0 1 1 Y=1
A=0
1 0 OFF
1 1
B=1
ON

Jul-13 ELEC343 - Digital Systems Design

 CMOS NAND Gate
A B Y
0 0 1 ON OFF
0 1 1 Y=1
A=1
1 0 1 ON
1 1
B=0
OFF

Jul-13 ELEC343 - Digital Systems Design

 CMOS NAND Gate
A B Y
0 0 1 OFF OFF
0 1 1 Y=0
A=1
1 0 1 ON
1 1 0
B=1
ON

Jul-13 ELEC343 - Digital Systems Design

 CMOS NOR Gate
A B Y
0 0 1 A
0 1 0
1 0 0 B
1 1 0 Y

Jul-13 ELEC343 - Digital Systems Design

 3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

Jul-13 ELEC343 - Digital Systems Design

 3-input NAND Gate
• Y pulls low if ALL inputs are 1
• Y pulls high if ANY input is 0

Y
A
B
C

Jul-13 ELEC343 - Digital Systems Design

ELEC343
Digital Systems Design

Fabrications

Lecturer: Dr. Yinan KONG

Office: E6A241 – Electronic Engineering
Email: yinan.kong@mq.edu.au
Phone: 9850 1094
Fax: 9850 9128

Jul-13 ELEC343 - Digital Systems Design

 CMOS Fabrication
• CMOS transistors are fabricated on silicon
wafer
• Lithography process similar to printing press
• On each step, different materials are
deposited or etched
• Easiest to understand by viewing both top and
cross-section of wafer in a simplified
manufacturing process

Jul-13 ELEC343 - Digital Systems Design

 Cross-section
• Typically use p-type substrate for nMOS
transistor
– Requires n-well for body of pMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Jul-13 ELEC343 - Digital Systems Design

 Inverter Cross-section

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

Jul-13 ELEC343 - Digital Systems Design

 n+ Transistor Dimensions

Jul-13 ELEC343 - Digital Systems Design

 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Metal to lightly-doped semiconductor forms
poor connection which has high resistance.
• Use heavily doped well and substrate contacts /
taps. A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Jul-13 ELEC343 - Digital Systems Design

 Latchup
• The npn transistor is formed from the n-
diffusion from the nMOS transistor, the p-
substrate, and the n-well.

Jul-13 ELEC343 - Digital Systems Design

 Latchup
• The pnp is formed by the p-diffusion in the
pMOS transistor, the n-well, and the p-
substrate.

Jul-13 ELEC343 - Digital Systems Design

 Latchup

bistable rectifier

Jul-13 ELEC343 - Digital Systems Design

 Latchup
• Power-up and external voltages can cause
substrate currents.
• These currents cause the substrate voltage Vsub
to rise, turning ON the npn transistor.
• This causes current to flow through Rwell,
lowering Vwell, and turning ON the pnp.
• The current through Rsub raises Vsub further,
causing a positive feedback loop.
• This latchup causes rapid failure or meltdown of
a circuit.
Jul-13 ELEC343 - Digital Systems Design
 Latchup
• The feedback loop in the bistable rectifier can
be overcome by minimising Rwel and Rsub.
• This is done by adding a p+ tap near gnd and a
n+ tap near vdd.
• The resistance is effectively lowered, like a
forward biased diode.
• When there is little voltage drop across Rwel
and Rsub the effective npn and pnp transistors
are left OFF.
Jul-13 ELEC343 - Digital Systems Design
 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap

Jul-13 ELEC343 - Digital Systems Design

 Cross-Section and Top
A

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

substrate tap well tap

Jul-13 ELEC343 - Digital Systems Design
 Detailed Mask Views
• Six masks n well

– n-well
– Polysilicon Polysilicon

– n+ diffusion n+ Diffusion

– p+ diffusion p+ Diffusion

– Contact Contact

– Metal
Metal

Jul-13 ELEC343 - Digital Systems Design

 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 Oxidation
• Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace

SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens when exposed to light
– Several drops of photoresist first
– The wafer is then spun at 3,000 rpm reducing the
puddle to an very uniform layer about 3 microns thick
– Photoresist is expensive ($1000/gal)
Photoresist
SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist
light

Photoresist
SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been
exposed

Photoresist
SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch

SiO2

p substrate

Jul-13 ELEC343 - Digital Systems Design

 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implantation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2

n well

Jul-13 ELEC343 - Digital Systems Design

 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of
steps

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers) Why that thin?
• Chemical Vapor Deposition (CVD) of silicon
layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Polysilicon Patterning
• Use same lithography process to pattern
polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Self-Aligned Process
• Use oxide and masking to expose where n+
dopants should be diffused or implanted
• N-diffusion forms nMOS source, drain, and n-
well contact

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing

n+ Diffusion

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 N-diffusion
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 N-diffusion
• Strip off oxide to complete patterning step

n+ n+ n+
n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 P-Diffusion
• Similar set of steps form p+ diffusion regions
for pMOS source and drain and substrate
contact

p+ Diffusion

p+ n+ n+ p+ p+ n+
n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+
n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Metallization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

Jul-13 ELEC343 - Digital Systems Design

 Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine
transistor size (and hence speed, cost, and
power)

Jul-13 ELEC343 - Digital Systems Design

 Feature Size
• Feature size f = distance between source and
drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing
design rules
• Express rules in terms of λ = f/2
– E.g. λ = 0.3 µm in 0.6 µm process

Jul-13 ELEC343 - Digital Systems Design

 Simplified Design Rules
• Conservative rules to get you started

Jul-13 ELEC343 - Digital Systems Design

 Inverter Layout
• Transistor dimensions specified as Width /
Length
– Minimum size is 4λ / 2λ, sometimes called 1 unit
– For 0.6 µm process, W=1.2 µm, L=0.6 µm

Jul-13 ELEC343 - Digital Systems Design

 Summary
• MOS Transistors are stack of gate, oxide,
silicon
• Can be viewed as electrically controlled
switches
• Build logic gates out of switches
• Draw masks to specify layout of transistors

Jul-13 ELEC343 - Digital Systems Design